TRST_N and RST_N Problems

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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rp181
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TRST_N and RST_N Problems

Postby rp181 » Wed Jan 05, 2011 5:56 pm

For prototyping, I had modules for the support hardware, for the XS1-L1 64LQFP. The power module works well by its self, 1v comes online after 3v3. As soon as the 1v line comes online, TRST_N and RST_N are brought low for a period of time, then jump back up to 3v3. This is only working by itself. When I connect 1v and 3v3 to the processor, TRST and RST fall low and never pull high again. I do have 10k pull up resistors on the TRST and RST lines, but they refuse to jump back to 3v3.
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Postby lilltroll » Wed Jan 05, 2011 7:27 pm

Do you use the old or NewDesign of XTAG2? (There was an issue regarding buffering or not, and about how much current the old XTAG2 could deliver on TRST and RST, (if I remember correctly)
Either the XTAG2 or your design should have a buffer to be safe in all situations, depending if they are connected to 1,2,3 or 4 pins on the receiving design (the MODE pins)
The XK-1 is buffered and works well with both old and new XTAG2's

Check the ERRATA (Last page) in
https://www.xmos.com/download/public/XS ... 2.1%29.pdf
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Postby rp181 » Wed Jan 05, 2011 7:41 pm

I missed that portion as I was using both Sparkfun's schematics and the XK-1. Luckily I ordered these parts, so I will give it a try. Is the buffer necessary on TMS and TCK too? I noticed that these pins were high when not connected to anything while scoping around.

So the buffer is effectively amplifying the signal so it is able to pull the pins high?
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Postby lilltroll » Wed Jan 05, 2011 8:01 pm

A buffer is typically able to provide more current.
Some pins on the L64 are guaranteed to provide 4 mA other 8mA, check 4.2 DC Characteristics.

In general, without knowing the details for the L64, the higher output current, the larger voltage deviation from the rail due to resistance in the output gates, (or some current limiting protection can interfere and suddenly change the voltage).

A buffer can deliver more current without a voltage drop down to critical detection levels - or the buffer has an lower output impedance.
With CMOS, typically the input impedance of a gate is high, so the current needed to supply them are tiny, but in this case the 100 ohms criteria exists, and if you have 4 100ohms in parallel you are down to 25 ohms.
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Postby rp181 » Wed Jan 05, 2011 8:14 pm

I am not paralleling any gates, the NC7WZ07 is a dual gate device. So what is this lower impedance coming from?

Thank you for the explanations!
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Postby lilltroll » Wed Jan 05, 2011 8:22 pm

Hmm, I do not have your schematic but, what is connected to

8 RST_N
25, 24, 23, 22 MODE[3:0]
26 TRST_N

in your design? Something is sourcing/sinking them, even if it's ground.
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Postby rp181 » Wed Jan 05, 2011 8:33 pm

I have all the MODE pins tied high/low respectively to set it to boot from JTAG, so those are tied to either IOVDD or GND.

I attached a picture of how TRST_N and RST_N are connected. This is how it is shown in the XK-1 schematics, minus the buffers and with pullup resistors. I will try it with the buffers, but I want to understand it rather than blindly connecting components together.
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Postby Folknology » Wed Jan 05, 2011 9:02 pm

What are the logic states (voltage) of the output of the RST pin on the NCP303LSN09 over the powerup and settle phase?

Also the 33pf cap should be in parallel with the 68K resistor, i.e. connected to the 1V output not 3v3 supply, its difficult to tell if this is the case.

It may be that the 1v supply is under voltage when you connect the L1, do you also have a decent cap on the 1v supply like a 10uf or 22uf as the core will take a lot of current initially? Also check for shorts on the 1v rail of the L1 board.

You could also try simulating the L1 core load using 3 x 10r (>100mwatt) resistors in parallel from 1 volt to ground as a dummy load to draw ~300ma and make comparative measurements for clues, this won't help with the dynamic issues and or noise however.
Last edited by Folknology on Wed Jan 05, 2011 10:04 pm, edited 4 times in total.
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Postby lilltroll » Wed Jan 05, 2011 9:14 pm

I have all the MODE pins tied high/low respectively to set it to boot from JTAG, so those are tied to either IOVDD or GND.

OK, it's a JTAG boot only device. Then the MODE pins cannot steal current from an CMOS output.
My concert was if you had active control over the MODE pins.
IOVDD and GND has a very low impedance, (much less than 1 ohm) to the feeding points of GND and IOVDD. Thus passive control never rises this problem I was talking about.
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Postby rp181 » Wed Jan 05, 2011 10:10 pm

What are the logic states (voltage) of the output of the RST pin on the NCP303LSN09 over the powerup and settle phase?
I am not sure, I will check. I am thinking it is 1v considering it is used as the input.
EDIT: Nvermind, it looks just like TRST_N and RST_N, it is pulled to 3v3, drops low, then jumps back up. But this is also staying low when the core is connected.
Also the 33pf cap should be in parallel with the 68K resistor, i.e. connected to the 1V output not 3v3 supply, its difficult to tell if this is the case.
It is, the picture crops out the 1v buck regulator. V+ signifies VDD, where +3v3 signifies IOVDD.
It may be that the 1v supply is under voltage when you connect the L1, do you also have a decent cap on the 1v supply like a 10uf or 22uf as the core will take a lot of current initially? Also check for shorts on the 1v rail of the L1 board.
I was seeing a lot of noise on the 1v line (the voltage was oscillating like a square wave), so now I have a 47uf capacitor on the 1v line.
You could also try simulating the L1 core load using 3 x 10r resistors in parallel from 1 volt to ground as a dummy load to draw ~300ma and make comparative measurements for clues, this won't help with the dynamic issues and or noise however.
That much current? My power supply shows a current draw of only 20ma. The power supply provides the 3v3 used for IOVDD, and for the 1v regulator. That makes me think the core is not drawing any current, though I see 1v when measuring the VDD line at the chip.
OK, it's a JTAG boot only device. Then the MODE pins cannot steal current from an CMOS output.
My concert was if you had active control over the MODE pins.
IOVDD and GND has a very low impedance, (much less than 1 ohm) to the feeding points of GND and IOVDD. Thus passive control never rises this problem I was talking about.
Yes, I figured I would worry about flash later as I am using a winbond chip. Can I just disconnect the flash when it is booting from JTAG? It would clear up the clutter for now ;)

EDIT: The regulator and reset is all drawing about 5ma, and there is a distinctive jump to 20ma when I connect IOVDD and VDD to the processor. So this means the GND pad is connected (I used kopr-shield, a conductive copper based viscous fluid). Not sure why its not drawing the amount of power it should. When scoping the 1v output, there is no distinctive cutoffs and restarts, so I do not think the regulator is being overloaded.

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