SP'I boot question, HW related

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
nisma
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SP'I boot question, HW related

Postby nisma » Sun Dec 20, 2009 2:51 pm

I don´t unterstand XMOS people why there have used X0A0 as MISIO and X0B0 as SS, where
the X0B0 is used for the 5bit Xlink and not free, but X0A0 is free. It make more sense to use
X0A0 as /CS in order to not interfere to the Xlink. This automatically limits the usage of 5bit
Xlink.

From the S1L manual:
Port Use
P1A0 SPI MISO
P1B0 SPI SS
P1C0 SPI SCLK
P1D0 SPI MOSI
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Folknology
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Postby Folknology » Tue Jan 05, 2010 11:20 am

This is also the same for the G4 boot spec, so I guess it is inherited from that. The question still stands however on those pin choices albeit less of an issue with the G4.

Still getting my head around these port quirks ;-)
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DrFingersSchaefer
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Postby DrFingersSchaefer » Tue Jan 12, 2010 7:34 pm

On the question of SPI Boot.

Has anyone tried using a SD or Micro SD card in it's SPI mode as a boot device ??
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TonyD
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Postby TonyD » Wed Jan 13, 2010 10:36 am

DrFingersSchaefer wrote: Has anyone tried using a SD or Micro SD card in it's SPI mode as a boot device ??
It would be great to boot from a SD or micro SD card.
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DrFingersSchaefer
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Postby DrFingersSchaefer » Wed Jan 13, 2010 3:09 pm

Yeah I was thinking the same.

Particularly the micro sd cards they would fit tidily onto a minimalist PCB in place of the hard wired chip and allow the swapping of software/function without downloading. I guess you could even write the image on any old PC with a card reader/writer.

If they will work that is.....

At the capacities they are available as for the prices they are well ahead of hard wired flash chips.

I guess it's a mass market thing.

I have got a couple of cheap micro sd cards on order (the sort with the micro to sd adapter that you can solder to and use as an improvised socket) with the intent of having a play at trying one on the xc-1. Just to see.

Wondered if anyone had beaten me to it ??

I am sure that getting the processor to interact with them is quite simple (even at full speed), the question is are they compatible enough with the hard-wired chips at stratup to function as a boot device.
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Postby TonyD » Wed Jan 13, 2010 11:21 pm

Theres a SD card and FAT16 project on xmoslinkers, but I have to admit I haven't really looked into it.

I'm guessing you could write a SD card boot loader and have it programmed into the OTP ROM to look for a SD card and load a program.
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paul
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Postby paul » Thu Jan 14, 2010 1:33 am

Booting directly out of an SD card is an interesting one - you could do it with a custom bootloader in the OTP or onboard flash. That is done on the XDK.

My only question about the boot from SD card in SPI mode directly thing is are the command sets the same?
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DrFingersSchaefer
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Postby DrFingersSchaefer » Tue Jan 19, 2010 9:44 pm

The micro sd cards I ordered have arrived, unfortunately unlike their picture on the web site I purchased them from they don't have the sd adaptor I was going to solder pins onto to use as a quick and dirty socket.

Going to have to nip out tomorrow and buy an adapter.
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Postby DrFingersSchaefer » Thu Jan 28, 2010 12:24 pm

OK got the adapter and soldered on a pin strip, So I now have a Micro SD Socket that I can plug into a socket soldered onto the XC-1, Just need to workout the connections for the SPI Boot, put an image on the card and see if it will work.

It is unlikely it will, but is worth a go.

Anyone know what the hack for the XC-1 is to stop it booting from the internal ROM and boot from external spi instead ??
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Folknology
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Postby Folknology » Thu Jan 28, 2010 3:16 pm

From the G4 system manual http://www.xmos.com/published/xsystem
The normal boot procedure is to first boot Core 0 from an external ROM or Flash
memory that is connected via an SPI interface. Each of the other cores is then
booted over the core’s channel-end 0 from core 0. This boot mode, called SPI-
boot, is enabled by setting pin SS XC0 BS0 to 0 (ground).
SPI pins =
P1A0 MISO
P1B0 SS
P1C0 SCLK
P1D0 MOSI
A READ command is issued with a 24 bit address 0x000000. Based on the
100MHz reference clock of the Xcore, an SPI clock rate of 2.5 MHz is used. The
clock polarity / phase is of 0 / 0.
The Xcore expects each byte to be transferred with the least-significant bit first.
Many programmers will write bytes into an SPI interface using the most signif-
icant bit first, and hence you may have to reverse the bits in each byte of the
image stored in the SPI device.
If a large boot image is to be read in, it is faster to first load a small boot-loader
that will read the large image using a faster SPI clock, for example 50 MHz, or
as fast as the flash device suppor ts.
If field-upgradeable firmware is required, a small boot-loader should be stored in
the first sector of flash memor y, followed by two boot-images star ting on sector
boundaries. The boot-loader should be written to first read the first image, and
on CRC failure boot from the second image. On upgrade, the first image is up-
graded first, followed by the second image. If the upgrade process is interrupted
at any point, there will always be a working boot image.
The SPI device will boot core 0 of the XS1-G4 only, the other cores must be
booted via channels.

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