XMOS variable instruction size not perfect for Spacecraft

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
User avatar
aspadistra
New User
Posts: 2
Joined: Mon May 10, 2010 5:05 am

XMOS variable instruction size not perfect for Spacecraft

Postby aspadistra » Fri Nov 12, 2010 12:30 pm

XMOS variable instruction size not perfect for Spacecraft ...

There is only 1 known spacecraft that uses Transputers, with thier fixed lenght instructions.

http://en.wikipedia.org/wiki/High_Energ ... t_Explorer

Variable length instructions pose problems for memory dumps (Voyager Program does them monthly), and when the instructions themselves have NO PARITY BIT ... the CPU or DSP may execute a faulty instruction blindly.

http://en.wikipedia.org/wiki/XCore

Instruction encoding
Instructions can use between zero and six operands. Most common arithmetic operations (such as ADD, SUB, MULT) are three-operand instructions based on a set of 12 general purpose registers. Three operands can be identified using no more than 11 bits, enabling a set of 13 frequently used 3-operand instructions to be encoded in 16 bits. Other instructions that are encoded in 13 bits are branch operations and common loads and stores.

Less frequently used instructions are encoded in 32 bits. These instructions encode instructions that operate on long immediate operands (far branches), on a large number of operands (for example long multiply which has 4 source and two destination operands) and instructions that are rarely used with fewer operands.

http://en.wikipedia.org/wiki/XCore_XS1-L1 -- AN IMPROVEMENT, BUT NOT PERFECT!

Instruction Set Architecture
Each thread has access to 12 general purpose registers, and a standard 3-operand instruction set is used for programming the thread. The instruction set is encoded densely, encoding most instructions in 16 bits, where 11 bits are used for specifying 3 operands, and 5 bits are used to encode the opcode. Less frequently used instructions are encoded in 32 bits. The instruction set is a load-store instruction set. All instructions execute in a single cycle. If an instruction does not need data from memory (for example, arithmetic operations), the instruction will prefetch a word of instructions.This acts like a very small instruction cache, but its behaviour can be predicted at compile time, making timing behaviour as predictable as functional behaviour.

++++++

The XMOS core designs are great for Earth, but ill suited for spacecraft.
ale500
Respected Member
Posts: 259
Joined: Thu Sep 16, 2010 9:15 am

Postby ale500 » Fri Nov 12, 2010 12:47 pm

x86 are even worst :) instructions are between 1 and 15 bytes long....

You know parity is not the great solution either... a CRC would be better :)

Edit: You know that a transputer is not the same as the xcore, don't you ? :mrgreen:
User avatar
snowman
Member
Posts: 13
Joined: Fri Dec 11, 2009 10:51 am

Postby snowman » Thu Mar 17, 2011 9:10 pm

Would redundancy help? Run identical code on two cores.

Altreonic have developed a fault tolerant controller using the XS1-L2. The slides talk about use in SIL4 applications:

http://www.altreonic.com/sites/default/ ... 10_2_0.pdf
http://wmec.files.wordpress.com/2010/07 ... rofile.pdf
User avatar
leon_heller
XCore Expert
Posts: 546
Joined: Thu Dec 10, 2009 10:41 pm
Location: St. Leonards-on-Sea, E. Sussex, UK.

Postby leon_heller » Thu Mar 17, 2011 10:51 pm

Plessey, Roke Manor, used one of my 16-module transputer systems for a fault-tolerant system. They'd ask a customer to pull out two or three modules at random and it would carry on working. The modules weren't designed for hot-swapping, but it didn't damage them.
User avatar
octal
XCore Addict
Posts: 228
Joined: Thu Jan 27, 2011 3:30 pm
Location: Argenteuil - France

Postby octal » Fri Mar 18, 2011 7:43 am

ale500 wrote:x86 are even worst :)
Don't remind me that there is something named X86!!! right now I don't understand how people who made 8051 arch does also X86 arch :?

ale500 wrote: You know parity is not the great solution either... a CRC would be better :)
But parity is more energy conservative!
User avatar
dave
Member++
Posts: 31
Joined: Thu Dec 10, 2009 10:11 pm

Postby dave » Fri Mar 18, 2011 2:24 pm

I don't know a lot about space applications and I don't understand what problem you are trying to solve. Can you explain?

The XCore instruction encoding is very similar to the transputer's. The transputer used single-byte instructions but had single-byte prefixing instructions that concatenated their operand with that of the following instruction. So instructions with long operands were built up as a sequence of single length instructions. In practice these prefix instructions were processed in the instruction buffer, so did not need to be executed in the normal way.

The XCore instruction encoding is based on 16-bit instructions. It also uses a prefix instruction (its most significant five bits are 11110) for the same purpose as the transputer's prefix instruction. It concatenates its 10-bit immediate operand with that of the next instruction. There is another prefix (its most significant five bits are 11111) which is used to supply the first three operands for the next instruction, allowing instructions with up to six operands. As in the transputer, these prefix instructions are processed in the instruction buffer.

Neither the transputer nor the XCore has parity bits or error checks on its instructions.

There were numerous fault-tolerant systems based on transputers including one developed for space use which used four processors which continuously checked each other - failing ones were reset. I imagine the same approach could be used with XCores.

Who is online

Users browsing this forum: No registered users and 3 guests