Some instructions (LDWCPL, LDAP*) use an u20 already; everything with a u16 uses a baselilltroll wrote:I believe that David responded along time ago that instructions can be fitted to adress larger memory-areas,
That's not my point. What I'm saying is that you usually (with enough ingenuity) can moldI agree a little with that either you need alot of RAM or you can do it with 64 kB.
Just as an example to play with: If you could buy a L4 with 4x64 kB SRAM or a L2 with 2x256 kB, for the same price, which one would sell best ?
something that uses e.g. 256kB to use 64kB instead; and it's totally impossible to have
more. I'm saying there aren't many problems for which e.g. 128kB is enough, but 64kB
Please note that it would either be slow or have performance per thread that is not independentOr if we had the choice of a L4 4x64 kB SRAM with a 256 Mbit of RAM of the top, using the on-die hi-speed links directly from the Switch, so all cores could adress the space with hi bandwith, and no output pins were stolen for memory connection.
of other threads and CPUs. This means that you can not use it the same way as you can
use the current on-chip memory; you have to use it more as a peripheral device.