USB ULPI on L series

[smuraski]

Is there a document which explains why we are restricted when using the ULPI interface? Is it possible to remap the ULPI interface to pins which don't interfere with the links? Is this a hardware or driver related issue?

[smuraski]

Also, why does the clock need to be 13MHz?

[lilltroll]

Also, why does the clock need to be 13MHz?

Every USB high-speed application must support a data rate of 480 Mb/s within ±500 ppm
(479.760 Mb/s to 480.240 Mb/s), meaning that you need an accurate clocksource.

Second, why exactly 13 MHz?
Since you do not program the internal PLL in the USB chip, they have to choose one crystal-frequency that can be transformed to the new frequencies used for the USB 1.X and USB 2.0 transmissions. My guess is that they of some reason chosen 13.00 MHz. A TI chip may have chosen 24.00 MHz instead.

[lilltroll]

Is there a document which explains why we are restricted when using the ULPI interface? Is it possible to remap the ULPI interface to pins which don't interfere with the links? Is this a hardware or driver related issue?

I believe that the ULPI Mode is a special HW support in the chip that cannot be remapped.

The XS1-L1 contains support for connecting to a USB transceiver using the UTMI+
Low Pin Interface (ULPI).
When using the XS1-L1 with ULPI, the ULPI signals must only be connected to specific
ports as shown in the following table.
When using ULPI, some ports on the same core are used internally and so are not
available for use by user software. These are shown greyed out in the table. The
available ports are shown in green. All ports on other cores are unaffected.
Note that this limitation only applies when the ULPI is enabled, the greyed out ports
can still be used before or after the ULPI is being used.
https://www.xmos.com/download/public/XM-000302-DG-1.pdf

[smuraski]

Appreciate your thoughts and answers...here is hopefully a better explanation of my inquiry.

My understanding is that the ULPI chip requires the 13MHz clock for its PLL and the IO ports on the XCORE are clocked from the ULPI clock output...this could imply that the XCORE 13MHz clock was chosen to reduce the BOM count/cost. Not sure if this limits the remainder of the IO clocking to 13MHz or if the IO clock is ramped up to 100MHz? I am very new to the XCORE architecture (less than a week) and I am still trying to merge all of the tech stuff into my head. So, ultimately I am trying to understand if the 13MHz is limiting the remainder of the chip IO capabilities? If I wanted to merge USB and Ethernet on single L2 chip, would the 13MHz still be required for the XCORE or could it be run at 25MHz and let the ULPI run at 13MHz?

[bearcat]

My understanding is the ULPI runs at around 60MHz back to the L1 (or L2). The actual clock speed to the XMOS is multiplied up by a PLL so it is configurable.

The USB3318 requires 13MHz, so we are generally stuck using that frequency. I had wondered if one could use the USB3317 at 26MHz, but got no response if it was a drop in replacement.

Using a single master clock would seem easiest, so using 13Mhz is the easiest to design with.

The XMOS does PLL mutiply up to 100Mhz for I/O as set in the .XN file. So the actually input frequency is not important.

Edited: for PLL input

[Berni]

As far as i know its ok to use the 24Mhz one. It seams to only be a mater of selecting the right chip. Only thing you have to look for is that the PLL can handle the input (max 25Mhz i think)