XEF232-1024-FB374-C40 and xlink3

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
SpacedCowboy
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XEF232-1024-FB374-C40 and xlink3

Postby SpacedCowboy » Wed Oct 21, 2020 4:54 pm

So I was planning on connecting an SDRAM to the XEF232 on tile 1, had all the pins worked out, and then read this discussion and found that tile 1's P16B isn't ideal because of the 8ma drivers. No problem, I have 4 tiles :)

For future expansion, I want a 5-way link off-chip as well as using xlink0 for the XTAG interface, and I was previously using xlink4 on Tile 2. Switching tiles 1 and 2 around to make things work smoothly with the SDRAM, I noticed there's a conflict on xlink3 because it shares pins with the boot-flash, and the data sheet says "An external 1K resistor must connect X0D01 to VDDIOL. X0D10 should ideally not be connected. If X0D10 is connected, then a 150 ohm series resistor close to the device is recommended".

Does that mean a 5-way link using xlink3 is out of the question ? Or is it still compatible with using the link ?

[edit: I found a port-configuration that works with xlink2, so this isn't as important as it was but I'm still curious if the link is useful in general]
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CousinItt
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Postby CousinItt » Mon Nov 02, 2020 8:33 pm

The XS1 Link Performance and Design Guidelines says
The master which boots from SPI cannot use X0LA in 5 wire mode (because some pins are the SPI I/O pins).
I don't know whether this also applies to later-generation devices.

There are a couple of risks I can think of in using the five-way link. Firstly other devices may need to boot from the XEF232 over a link, so the flash and links could be in use simultaneously. Most current data sheets only show booting over link 0 (at the bootee end) using two wires, but other information (e.g. on this site) shows boot modes 5, 6 and 7 all with 5-way links. Maybe boot code has to remain compatible with these older modes, even if they are no longer encouraged.

Secondly the link would use both the chip select and clock of the flash. The data pins would need to be put into a safe state (assuming one is available) to ensure that the flash wasn't corrupted accidentally.

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