I/O timing with set_port_inv function

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Joined: Tue May 19, 2020 2:27 pm

I/O timing with set_port_inv function

Postby takaaki39ra1 » Tue May 19, 2020 3:15 pm

Hello Everyone,

I plan to use a Non source-synchronous clock scheme to drive some output ports on xCORE200.
I know "I/O timings for xCORE200" describes the detail IO timing including above mentioned scheme.
In my project, I plan to invert the polarity of a clock input port and some data output ports by using "set_port_inv" function which is defined in XS1 Library.
Even in this case, can I still refer T(CLKtoDATA) value described in the document "I/O timings for xCORE200"?
I'm afraid that inverting the polarity may insert some additional propagation delay on top of the T(CLKtoDATA) value described in the document "I/O timings for xCORE200".
If above my assumption is correct, how can I estimate the correct T(CLKtoDATA) value for my application?

I hope someone give me advise.

Best Regards,
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Joined: Thu Jun 10, 2010 11:43 am

Postby mon2 » Wed May 20, 2020 10:11 am

Hello. A few suggestions:

1) download and study the XMOS Programming guide, section 6.7 page 68 and onwards.


It is possible for your code to be synchronized to an external clock for the sampling of your I/O data. You can even count the clock cycles before a trigger captures such data or trigger on rising / falling external clock edges. Numerous examples inside this document. All software based. Xmos is the closest solution to fpga use.

2) review on how to use the xscope and simulator tool so you can synthesize the hardware before building. Here you can visualize the delays for your project. These tools are available in your free IDE toolchain.

Hope this helps.

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