I made a schematic for the XS1-L1 for a mini proto module before I integrate directly on board. I was wondering if someone could look over it, and see it looks good.
It will be programmed by the XTAG, no IO is broken out in the schematic.
I was wondering about the MODE pins, how should I configure this for automatic switching between JTAG and FLASH, like the XC-1A does?
I attached an EAGLE schematic.
Minimalist XMOS Board- would like someone to review
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rp181
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Minimalist XMOS Board- would like someone to review
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Folknology
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HI rp
You may want to post a pdf of that schematic as many folks do not use eagle.
I took a look and here is some feedback:
You appear to be using an LDO regulator for the 1 volt rail in a similar fashion to the Sparkfun board. This is likely to get quite warm and a switcher would be a better and more efficient choice. Also you need to be careful about power sequencing, even though the 1v is fed from the 3.3 this does not guarantee the power sequence timings highlighted in the XMOS Design Advisory No. DAXS1L01A100610R , this issue is also referred to in the L1 hardware design checklist. This can be fixed by use of a power good signal or even an RC + scmitt trigger as some have used.
Although the XK1 has a bad power section example its use of mode pins is probably suitable for your usage so worth checking out that schematic for mode pins config as an alternative to jumpers.
*Update Couple of other things , don't forget the decoupling you will need at least 8*100nf, one on each of the supply pins. I'm no sure what you are doing with pins X0D4-X0D7 are they connected together or is this a eagle grouping thing?
regards
Al
You may want to post a pdf of that schematic as many folks do not use eagle.
I took a look and here is some feedback:
You appear to be using an LDO regulator for the 1 volt rail in a similar fashion to the Sparkfun board. This is likely to get quite warm and a switcher would be a better and more efficient choice. Also you need to be careful about power sequencing, even though the 1v is fed from the 3.3 this does not guarantee the power sequence timings highlighted in the XMOS Design Advisory No. DAXS1L01A100610R , this issue is also referred to in the L1 hardware design checklist. This can be fixed by use of a power good signal or even an RC + scmitt trigger as some have used.
Although the XK1 has a bad power section example its use of mode pins is probably suitable for your usage so worth checking out that schematic for mode pins config as an alternative to jumpers.
*Update Couple of other things , don't forget the decoupling you will need at least 8*100nf, one on each of the supply pins. I'm no sure what you are doing with pins X0D4-X0D7 are they connected together or is this a eagle grouping thing?
regards
Al
Last edited by Folknology on Fri Oct 01, 2010 12:56 pm, edited 3 times in total.
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skoe
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Can you please also attach a PDF or PNG?
I can confirm what Folknology said: A linear regulator for 1V becomes too hot and wastes lots of energy. Because of that my previous board was the first one with a switching regulator (I'm a software developer normally...). I simply copied the reference design with Digikey number NCP1521BSNT1GOSCT-ND, works great and is not too expensive.
I can confirm what Folknology said: A linear regulator for 1V becomes too hot and wastes lots of energy. Because of that my previous board was the first one with a switching regulator (I'm a software developer normally...). I simply copied the reference design with Digikey number NCP1521BSNT1GOSCT-ND, works great and is not too expensive.
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segher
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Look at the XC-1A schematics; you pull a mode pin based on TRST.rp181 wrote:I was wondering about the MODE pins, how should I configure this for automatic switching between JTAG and FLASH, like the XC-1A does?
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rp181
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Thanks for the suggestions. I did base it almost entirely off of the sparkfun board. Let me take a look at the ref designs and check that power sequencing, thanks for the switcher rec.
I attached a png.
EDIT: I think I will go RC + schmitt trigger. What is a suggested capacitor size?
Are all 8 decoupling capacitors necessary? I will be sure to power the board with clean power. Should I position them together or around the XS1?
The grouping of the pins was me, just to mark the Xlinks.
I attached a png.
EDIT: I think I will go RC + schmitt trigger. What is a suggested capacitor size?
Are all 8 decoupling capacitors necessary? I will be sure to power the board with clean power. Should I position them together or around the XS1?
The grouping of the pins was me, just to mark the Xlinks.
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Bianco
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A cap next to (as close as possible) each supply pin is highly recommended just like on any other digial IC.rp181 wrote:
Are all 8 decoupling capacitors necessary? I will be sure to power the board with clean power. Should I position them together or around the XS1?
Don't group them together! (read http://www.seattlerobotics.org/encoder/ ... asics.html to know more about decoupling caps)
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rp181
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I added decoupling capacitors on all the power input. I think I will use the 1 volt reg from the ref design:
http://search.digikey.com/scripts/DkSea ... T1GOSCT-ND
On the reference design, does that have correct power sequencing? If so, what part does it?
http://search.digikey.com/scripts/DkSea ... T1GOSCT-ND
On the reference design, does that have correct power sequencing? If so, what part does it?
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Folknology
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The enable input (EN pin 3) on the 1 volt switcher is normally activated by a power good (PG) signal from the 3.3v regulator. This ensures that the 1volt rail isn't brought up until 3.3v is stable. If your 3.3v regulator doesn't have a power good output signal you have to create one yourself.
regards
Al
regards
Al
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rp181
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Ok. Is that how the power sequencing is done, with a PGOOD signal?
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rp181
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Hello,
I switched the 1v reg to a NCP1521B, and used the circuit the hardware ref design did (but with a 3v3 input). For power sequencing, how would one of these:
http://www.analog.com/static/imported-f ... CMP361.pdf
with the output tied to enable of the 1v0 reg work, if the input was tied to 3v3 with a 7.25 voltage divider? The input would be loaded with a capacitor/current limiting resistor.
EDIT: The threshold for the NCP1521B enable pin is .7v. Could I just use a charging capacitor on that w/ a current limiting resistor?
I switched the 1v reg to a NCP1521B, and used the circuit the hardware ref design did (but with a 3v3 input). For power sequencing, how would one of these:
http://www.analog.com/static/imported-f ... CMP361.pdf
with the output tied to enable of the 1v0 reg work, if the input was tied to 3v3 with a 7.25 voltage divider? The input would be loaded with a capacitor/current limiting resistor.
EDIT: The threshold for the NCP1521B enable pin is .7v. Could I just use a charging capacitor on that w/ a current limiting resistor?