Hi leif.

Glad you got it working. I did an xobjdump of some code of mine, here's what I got for fl_disconnect

Code: Select all

```
<fl_disconnect>:
0x0005c250: 00 f0 42 77: entsp (lu6) 0x2
0x0005c254: 03 f0 c4 d0: bl (lu10) 0xcc4 <fl_int_qspiFinish>
0x0005c258: 00 68: ldc (ru6) r0, 0x0
0x0005c25a: c2 77: retsp (u6) 0x2
```

So all it does is call fl_int_qspiFinish and then return 0, indicating success... here's fl_int_qspiFinish

Code: Select all

```
<fl_int_qspiFinish>:
0x0005dbe0: 00 f0 40 77: entsp (lu6) 0x0
0x0005dbe4: 1b f0 18 58: ldw (lru6) r0, dp[0x6d8]
0x0005dbe8: 94 a7: mkmsk (rus) r1, 0x4
0x0005dbea: c4 ae: out (r2r) res[r0], r1
0x0005dbec: f0 87: syncr (1r) res[r0]
0x0005dbee: 1b f0 5b 58: ldw (lru6) r1, dp[0x6db]
0x0005dbf2: 40 e8: setc (ru6) res[r1], 0x0
0x0005dbf4: 00 e8: setc (ru6) res[r0], 0x0
0x0005dbf6: 1b f0 19 58: ldw (lru6) r0, dp[0x6d9]
0x0005dbfa: 00 e8: setc (ru6) res[r0], 0x0
0x0005dbfc: 1b f0 1a 58: ldw (lru6) r0, dp[0x6da]
0x0005dc00: 00 e8: setc (ru6) res[r0], 0x0
0x0005dc02: c0 77: retsp (u6) 0x0
```

It looks to me like it's disabling some resources, probably the clock and IO for the quad spi. I get that by looking at fl_int_qspiInit() because it seems to just set up these resources, see below. So it seems to me that's not going to have any effect on the data in the FLASH itself -- it really shouldn't matter to keep them enabled, so long as you don't need to use those resources elsewhere.

Code: Select all

```
<fl_int_qspiInit>:
0x0005db90: 00 f0 42 77: entsp (lu6) 0x2
0x0005db94: 1b f0 58 58: ldw (lru6) r1, dp[0x6d8]
0x0005db98: 48 e8: setc (ru6) res[r1], 0x8
0x0005db9a: 00 f0 86 68: ldc (lru6) r2, 0x6
0x0005db9e: d9 fe ec 0f: setclk (lr2r) res[r1], r2
0x0005dba2: 1b f0 99 58: ldw (lru6) r2, dp[0x6d9]
0x0005dba6: 88 e8: setc (ru6) res[r2], 0x8
0x0005dba8: 00 f0 c6 68: ldc (lru6) r3, 0x6
0x0005dbac: de fe ec 0f: setclk (lr2r) res[r2], r3
0x0005dbb0: 1b f0 da 58: ldw (lru6) r3, dp[0x6da]
0x0005dbb4: c8 e8: setc (ru6) res[r3], 0x8
0x0005dbb6: 80 f0 cf e8: setc (lru6) res[r3], 0x200f
0x0005dbba: e0 6a: ldc (ru6) r11, 0x20
0x0005dbbc: 5f ff ec 27: settw (lr2r) res[r3], r11
0x0005dbc0: 00 f0 c6 6a: ldc (lru6) r11, 0x6
0x0005dbc4: 5f ff ec 0f: setclk (lr2r) res[r3], r11
0x0005dbc8: 9c a7: mkmsk (rus) r3, 0x4
0x0005dbca: cd ae: out (r2r) res[r1], r3
0x0005dbcc: f1 87: syncr (1r) res[r1]
0x0005dbce: 1b f0 5b 58: ldw (lru6) r1, dp[0x6db]
0x0005dbd2: 48 e8: setc (ru6) res[r1], 0x8
0x0005dbd4: 30 47: zext (rus) r0, 0x8
0x0005dbd6: d1 16: setd (r2r) res[r1], r0
0x0005dbd8: 08 90: add (2rus) r0, r2, 0x0
0x0005dbda: 00 f0 2f d7: bl (lu10) -0x32f <configure_port_clock_output>
0x0005dbde: c2 77: retsp (u6) 0x2
```