xCORE-200 PLL specification?

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
chouston00
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xCORE-200 PLL specification?

Postby chouston00 » Mon Jun 05, 2017 8:03 pm

Is there any additional information on the PLL in the xCORE-200 beyond what's in the datasheet (we're using the XEF216)? Specifically, I'm interested in

1) cycle-to-cycle input jitter tolerance
2) minimum/maximum duty cycle of the input clock

Thanks!
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andrewxcav
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Postby andrewxcav » Fri Jun 09, 2017 8:36 pm

Assuming that the PLL in question is the CS2100 (and I think it has to be):

Jitter plots are on page 8 of this PDF:

https://d3uzseaevmutz1.cloudfront.net/p ... OTP_F3.pdf

And It looks like the input clock needs to be between 45% and 55%
chouston00
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Postby chouston00 » Fri Jun 09, 2017 9:20 pm

Sorry - I meant the actual PLL in the xmos device :).
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andrewxcav
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Postby andrewxcav » Mon Jun 12, 2017 4:10 pm

I can't find anything on duty cycle, but the jitter is on page 26 (27th page of the PDF) of this data sheet:

http://www.xmos.com/download/private/XU ... .12%29.pdf

And is specified as having a maximum (pk-pk) jitter of 2% of the clock period.

What sort of oscillator are you looking to use?

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