CPU recommendation

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
Biquad
Junior Member
Posts: 6
Joined: Wed May 24, 2017 11:38 am

CPU recommendation

Postby Biquad » Wed May 24, 2017 12:35 pm

Hello,
i need an advice which simple pinout cpu should i use for the following specs:
I need : I2S IN (send to PC) and I2S OUT (DAC), S/PDIF OUT maybe S/PDIF IN if possible , ( 24Bit / 192k ) over USB Audio Class 2

I have thought about the XU208-128-TQ64

What do you think ?

Best regards
Andy
User avatar
infiniteimprobability
XCore Expert
Posts: 874
Joined: Thu May 27, 2010 10:08 am
Contact:

Postby infiniteimprobability » Thu May 25, 2017 9:58 am

A basic config may fit in that device but it's close and depends on how many channels you need and what flash you want to use. Can you elaborate on channel count?
AlexAdvice
Experienced Member
Posts: 85
Joined: Sun Feb 23, 2014 11:30 am

Postby AlexAdvice » Thu May 25, 2017 3:33 pm

Biquad wrote:maybe S/PDIF IN if possible


How would you think to implement SPDIF IN - with external PLL or with software ASRC?
User avatar
infiniteimprobability
XCore Expert
Posts: 874
Joined: Thu May 27, 2010 10:08 am
Contact:

Postby infiniteimprobability » Thu May 25, 2017 5:35 pm

SPDIF in by default is supported using an external PLL( CS2x00) to recover the clock. ASRC is possible and the IP is available but that will take a bigger device with more MIPS. Also, be aware that 192kHz input is not supported over optical.

viewtopic.php?t=5587

Any word on my previous question? I can't advise on your original request without details.
Biquad
Junior Member
Posts: 6
Joined: Wed May 24, 2017 11:38 am

Postby Biquad » Thu May 25, 2017 5:46 pm

Hello,
big thanks for all replys.
- AlexAdvice
you are right its not easy to recover the SPDIF IN clock using an pll so i have canceled this idea.

-infiniteimprobability
I have made the decision to use only one UAC2 class channel for 24b / 192k downstream to pc at first. Inputpins to Xmos will be all I2S lines mclk,sdata,LRc....
and one SPDIF TX output pin for an transformer. Maybe a CDC class would also be nice for control purposes via an terminal program.
Because of the limited boardspace i would prefer an internal flash and a simple reference project as a start ;)

Big thanks for helping me out selecting the right one.
User avatar
infiniteimprobability
XCore Expert
Posts: 874
Joined: Thu May 27, 2010 10:08 am
Contact:

Postby infiniteimprobability » Fri May 26, 2017 9:37 am

OK, so for 1b ports (the valuable commodity) that's:

MCLK
BCLK
LRCLK
DATAOUT
SPDIF OUT (don't forget to resynch on MCLK for min jitter)

I2C can be handled by 4b port OK so no probs.

The TQ64 has 7 x 1b ports available with USB enabled and boot in QSPI mode or 5 in SPI mode (although you can mux/reuse SPI with some planning). Either way you are covered.

I strongly reccomend you use this document. We use it internally for I/O planning.

https://www.xmos.com/published/xcore-20 ... es-portmap

Thread/Memory-wise you have plenty to spare the XU208 (TQ64) is a good fit. The XUF208 (TQ64) includes FLASH so that sounds like a good choice..

You can certainly add CDC to the ref design. There is a gotcha which this thread should help you around viewtopic.php?f=8&t=5025&p=25828#p25828
Biquad
Junior Member
Posts: 6
Joined: Wed May 24, 2017 11:38 am

Postby Biquad » Sat May 27, 2017 12:10 am

Hello, thanks for the SPDIF hint and the exel sheet,
sorry little meeting update, according to the team we need for the ADC /DAC box :
UAC-2 : One "I2S into xmos stereo L/R channel downstream to pc"(M,B,LR,Data, SPDIF OUT) 24b/192k and
One "UAC2 to I2S stereo upstream from pc to the dac"(M,B,LR,Data).24b/ >=192k /368
The XU208 TQ64 is hard to get imo at digikey. 12 weeks delay on the XUF.

Do you have an other xmos cpu option ? We prefer TQ48/ 64 external flash is also possible. XS1 is available.

Big thanks
Biquad
Junior Member
Posts: 6
Joined: Wed May 24, 2017 11:38 am

Postby Biquad » Sat May 27, 2017 9:21 pm

Thank you for the hint about the SPDIF mclk resync,
we had a meeting and have made the decision to extend it to a ADC DAC box
therefore we need an 24b / 192 k or more 768k upstream as UAC2 USB to I2S interface and the previous mentioned I2S downstream.
As far as i can read we need 4b port for the UAC2 downstream and a 4b port for the UAC2 upstream to the DAC. So 8 x 1b ports in usb mode ?
Is it possible to run the up and downstream with differend samplerates on UAC2?

The XUF is hard to get and have an 12 weeks order delay on digi . We prefer an TQ64 maybe with an external flash. The XS1 is available in good quantities.
What cpu is a good start ?

Big thanks
Andy
User avatar
infiniteimprobability
XCore Expert
Posts: 874
Joined: Thu May 27, 2010 10:08 am
Contact:

Postby infiniteimprobability » Thu Jun 01, 2017 8:03 am

Thank you for the hint about the SPDIF mclk resync,
we had a meeting and have made the decision to extend it to a ADC DAC box
therefore we need an 24b / 192 k or more 768k upstream as UAC2 USB to I2S interface and the previous mentioned I2S downstream.

I'm not 100% clear - what is the 768k requirement? 768kHz audio?
How many channels of audio do you need?

As far as i can read we need 4b port for the UAC2 downstream and a 4b port for the UAC2 upstream to the DAC. So 8 x 1b ports in usb mode ?
Is it possible to run the up and downstream with differend samplerates on UAC2?

You can use 4b ports but it's not standard in the ref design. Normally it uses a 1b port per 2 channels (I2S) or a 1b port for 8 channels (TDM).

The XUF is hard to get and have an 12 weeks order delay on digi . We prefer an TQ64 maybe with an external flash. The XS1 is available in good quantities.
What cpu is a good start ?

XS2 is recommended for new designs. XU208-128-TQ64 or similar is fine, but please confirm the channel count..

Big thanks

no probs!
User avatar
infiniteimprobability
XCore Expert
Posts: 874
Joined: Thu May 27, 2010 10:08 am
Contact:

Postby infiniteimprobability » Thu Jun 01, 2017 1:42 pm

Hello again,
as you can see i have strong problems to figure everything out. Maybe a graphical configuration tool like the STM32cube would be nice.
Yes if its possible we need up to 768k /24b stereo audio USB to I2S converter for the DAC and 192k/24b stereo audio I2S send down to PC.


Ah OK. 768KHz has been achieved by others (I have not tried it) so that should be OK. Be aware that the reference design by default is single clock domain. So your up and down streams will share the same LRCLK. The windows driver (Thesycon) has a single clock domain limitation too.
I have had multiple clock systems working (macos/linux) but it's not a standard feature and requires some work.

All with UAC2.

It will need to be because >12Mbps

If possible all at the same time. So we need a minimum of two differend I2S in / output ports.
I think for the ADC I2S in slave mode we need Mclk, LRclk,Sdata, Sclk inputs to xmos
I2S DAC needs Mclk, Biclk, Sdata, LRclk xmos outputs

As per previous post, a single tile (eg. XU208) device has 7 spare 1b ports if you use QSPI boot flash so you can calculate port usage from there!

Return to “Processors”

Who is online

Users browsing this forum: No registered users and 6 guests