XHRA-2HPA-TQ64 - Events for GPI pins? How to use them even?

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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mon2
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Re: XHRA-2HPA-TQ64 - Events for GPI pins? How to use them even?

Postby mon2 » Fri Apr 14, 2017 2:21 am

OMG Caleb - believe you are spot on! Not sure how we missed this comparison. Suspecting we stopped after reviewing the TQFP64 packaged XS1 devices.

So....why can we not use the JTAG interface to flash the target flash with the XHRA-2HPA ? In using the NC pins which should be JTAG as noted in the XU208-xxx-TQ64, the external flash should be able to be programmed.

Has anyone attempted to use JTAG (NC marked pins) with the XHRA-2HPA devices ? I think the difficult part will be to interface with the fine pitch pins. Better to solder a blank onto a TQFP to DIP PCB and then attempt all such testing.

Curious to hear of any such reviews.
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Caleb
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Postby Caleb » Fri Apr 14, 2017 10:04 pm

I haven't tried this because we just decided to use the XU208-128-TQ64. But if we had used the XHRA-2HPA then we were going to hook an xtag connector to those NC pins and give it a try - to see if it would work. I assumed that they were the same part though maybe there's some different boot program int the XRA-2HPA or maybe some code in the OTP memeory.
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Bianco
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Postby Bianco » Sat Apr 15, 2017 2:21 am

Caleb wrote:Not the XU208-256-TQ64 ? (or XU208-128-TQ64)
Absolutely certain it is one of those two. Of course if you sell preprogrammed chips, you want to disable the JTAG interface.
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Caleb
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Postby Caleb » Mon Apr 17, 2017 9:03 pm

Isn't it the case though that the XHRA-2HPA boots from a flash? All of the XMOS processors are pre-programmed in that there is a boot-loader program in ROM that loads a program into RAM from a flash device that is connected to the specified pins, configures the PLL according to parameters found in that program and launches execution. It seems that the same must be true for the canned program. But that program is highly parameterized at run-time from the pseudocode configuration file that I guess is stored in the designated data space in the flash. whereas the user-programmable chip's audio program is mostly parameterized at compile-time.
Now maybe the JTAG interface is disabled or maybe it's just not documented. I wouldn't be surprised if it's all the same chip except the OTP memory has a program that runs at boot-time and makes it behave differently from a normal device. It'd be interesting to see whether the XTAG interface, if connected to those NC pins, could communicate and run a program.

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