A clock frequence can be adjust from 100Mhz to 400Mhz step by 20Mhz?

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
oayzw
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A clock frequence can be adjust from 100Mhz to 400Mhz step by 20Mhz?

Postby oayzw » Tue Mar 07, 2017 5:36 am

Hi there,
I have no idea for a clock frequence can be adjust from 100Mhz to 400Mhz step by 20Mhz on xCORE-200 eXplorerKIT .

Does eXplorerKIT have to connect any componet /module to generate the clock?

any ideas are welcome!


Thank you very much!
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xsamc
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Postby xsamc » Tue Mar 07, 2017 10:29 am

Hi oayzw,

If you're looking to adjust the system clock, the xCORE-200 Clock Frequency Control document details how to adjust the PLL that drives it.

Section 4 of the above document describes how rapidly the frequency can be stepped while running.

Cheers,
Sam
oayzw
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Postby oayzw » Wed Mar 08, 2017 5:21 am

HI xsamc,

I read the document carefully after your reply.
The system clock connect pll to other clocks like ref clk and tile clk.
It Means that:
Timing of pins that connected to ref clk will change after pll frequence changed.
i do not expect this.

i mean a pin output a clock that's frequence can be adjust from 100Mhz to 400Mhz step by 20Mhz.
just like a separate configurable pll moudle.

thank you very much!
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xsamc
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Postby xsamc » Wed Mar 08, 2017 10:14 am

Ah sorry, so you want to output a clock on a pin. This won't be easy to achieve on an xCORE, as even if the 500MHz system clock was connected to the port, you could only output at up to 250MHz. The dividers in the clock blocks will not be able to create 20MHz steps either, but you may be able to get around this by also adjusting the PLL settings and rebooting between frequency steps.

This document gives an overview of configuring ports and clock blocks.

Cheers,
Sam
oayzw
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Postby oayzw » Wed Mar 08, 2017 11:32 am

Hi Sam,

how long does it take for reset to rework ?
Thank you very much!
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mon2
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Postby mon2 » Wed Mar 08, 2017 1:11 pm

Why not use an external PLL and dial up your clock value using I2C ? That would be the best option.

Also, what is the specification of this external clock generator ? You must be very careful of the clock traces at such high speeds. How far away is the device that will use this high speed clock value ?

The PCB, at the very least should be 4 layers and follow high speed digital design rules.

For devices to support this range, you can consider some of the Analog DDS devices (AD9910, etc.) and there are a mix of PLL devices on the market that claim to support these values.
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xsamc
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Postby xsamc » Wed Mar 08, 2017 2:12 pm

The time taken to reboot would depend on the number of xCORE nodes in the system, and the size of the binary (application) which is being booted (as the binary must be read in from SPI flash).

Cheers,
Sam
oayzw
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Postby oayzw » Thu Mar 09, 2017 2:27 pm

mon2 and Sam,

thank you very much!

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