XS1-L4A with 24.576MHz osc

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nico
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XS1-L4A with 24.576MHz osc

Postby nico » Wed Mar 01, 2017 1:59 pm

Hi,

I am wondering if it is possible to use a 24.576MHz quartz as the main clock source instead of a 24MHz or 25MHz. I can't find the answer on the net or on the forum ...
The application would be a SPDIF to I2S converter using a XS1-L4A-64-TQ48-C4. The chip will run some custom code for our application and I would like to have the cheapest possible BOM. The idea is to output the I2S MCLK directly from the Master clock.

Thanks for your advices !

Regards,
Nicolas
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mon2
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Postby mon2 » Wed Mar 01, 2017 2:20 pm

Hello again Nicolas. Not an audio person but from memory, believe that most audio designers are using the pre-configured PLL from SiLabs. That is, XMOS has built up a factory programmed PLL from SiLabs and this part is available from Digikey and perhaps other sources. The PLL upon power up will offer the required clock outputs for your project. You can then use I2C interface to alter the clocks at any time but that is optional. Reference the full part number shown in the XMOS schematics to locate the programmed part. Otherwise, you will have to generate a similar device using the free tool (Clock Builder) from SiLabs' website.

On the topic of costs, the crystal is available for about $ 0.06 USD from Shenzhen, China

< you can also order through their Aliexpress store >

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Postby mon2 » Wed Mar 01, 2017 2:23 pm

viewtopic.php?f=7&t=4599

viewtopic.php?f=8&t=5092&view=next

If you will be using USB with this project then you will need 24 Mhz otherwise, test and see if the alternate clock value is suitable for your IP. Often the XMOS code is tied to the recommended clock value.
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Postby nico » Wed Mar 01, 2017 2:34 pm

Thanks a lot for the pointer I think that you talk about SI5351A-B04486-GT which is less than 1$ (but it still needs a crystal ...)
And thanks for the crystal price, I thought it was more expensive.
I only need 48kHz I2S (no USB) so I may add a crystal given the cost.
And yes, I plan to test that on a startkit.
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Postby nico » Wed Mar 01, 2017 2:35 pm

Oh I replied before seeing your second answer ...
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Postby Caleb » Wed Mar 01, 2017 11:31 pm

To implement a S/PDIF receiver you need a PLL to adapt to the exact speed of the incoming signal. Fixed crystal is probably not adequate.
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Postby akp » Tue Apr 04, 2017 6:25 pm

That's true unless you use ASRC which is the whole point of https://www.xmos.com/support/appnotes/AN00231
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Postby Caleb » Tue Apr 04, 2017 8:28 pm

akp wrote:That's true unless you use ASRC which is the whole point of https://www.xmos.com/support/appnotes/AN00231


In that case, a 24.576MHz oscillator may work just fine if you only need to decode 48kHz. It gives you the Mclk you need to operate the IIS at the correct FS.
For the S/PDIF receiver at 48kHz, normally the reference clock is 100MHz and the decoder is sampling the S/PDIF input at 12.5MHz, which is just the reference clock / 8. You'd have to look at the parameters for configuring the system clock (and the derived reference clock) and determine how close you can get to 100MHz. Probably not exactly 100MHz, I think you'd probably want to chose for a little higher rather than lower. The decoder already fails to meet the S/PDIF specification for high frequency jitter rejection. The higher the sampling frequency the better the rejection. You can always set the system and reference clocks a little high in the .xn file. 101.5MHz reference clock generally takes care of S/PDIF decoding problems where the source is poor quality with high period jitter as is becoming very common these days. You might want to get a Chromecast audio and look at how bad the jitter is. The XMOS decoder will not handle it at 96kHz unless you run the reference clock high.
The problem you run into with increasing the reference clock: if it's much higher than 101.5MHz then you lose ability to decode 44.1kHz (as well as 88.2 and 176.4). The decoder only works in the range of 4 - 4.5 samples per bit of S/PDIF data +/- depending on amount of jitter in the signal. So with the normal 100MHz reference clock divided to 12.5MHz, you can decode approximately 43.403kHz-48.828kHz (if there were no jitter). You can just multiple those frequencies by 2 or 4 for the 88.2/96 and176.4/192kHz sample rates but know that jitter inevitably becomes a higher % of the bit period with higher FS.

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