Dual XE216 System Intermittent Startup Issues

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CrAzIaNhAx
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Dual XE216 System Intermittent Startup Issues

Postby CrAzIaNhAx » Wed Dec 21, 2016 8:25 am

Hi All,

We have two XE216 running on our custom PCB. One boots from QSPI and the other boots via XLink. After the system runs for a period of time, a reset or power cycle is performed and the Xmos' fail to boot up correctly and run the programmed application. We believe the problem is temperature related as it seems to occur when the Xmos reach 40C+ and takes longer to recover at higher temperatures.

To try figure out why the Xmos does not boot I have tried reading the registers using xgdb for a successful and unsuccessful boot. I have used the xlreg script provided by Colin from this thread.

http://www.xcore.com/forum/viewtopic.ph ... 2b79f2a1f5

Reading the registers from an unsuccessful boot shows that the PLL Reg has been configured incorrectly. Is this calculated on power up? I don't understand how this could be so because the clock signal look fine on the scope and the clock circuit is not powered down on a reset. Attached are debug outputs and xn files. Hopefully someone can make more sense of this.

Thanks,
Daniel
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mon2
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Postby mon2 » Wed Dec 21, 2016 1:45 pm

A few general thoughts on this topic:

1) Is the same circuit always stable at room temperature ?

2) How is the stability of your power supply at the higher temp ?

3) How is the reset & power sequencing at room temperature ? At the higher temps ?

4) What caps are used in this design ? dielectric = x5r ? If X5r, shift to X7r and test again. Avoid electrolytics and tantalums - consider ceramics wherever possible.

5) Can you post your power supply and power sequencing circuit for a review ?

6) Trusting the PCB assembly to be sound ?

If the clock is deemed to be stable, our focus would be on the power up / power sequencing and reset logic for this review.
Redeye
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Postby Redeye » Wed Dec 21, 2016 10:06 pm

I agree with what mon2 says. From previous experience with a similar problem, reset circuitry would be where I'd start looking. Particularly :

- Are !RST and !TRST being held low for long enough?
- Are the reset lines being pulled right down to GND, or are they not getting quite low enough?
- Is the power supply sequencing still within the timing spec at higher temperatures?
CrAzIaNhAx
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Postby CrAzIaNhAx » Thu Dec 22, 2016 12:16 am

Hi Mon2 & Redeye. Thank you for the quick reply and your suggestions. Please note that this problem occurs when we power cycle the device or pull the reset line low.

1) Is the same circuit always stable at room temperature ?
The Xmos is running as normal at room temperature before reset or power cycle.

2) How is the stability of your power supply at the higher temp ?
We have monitored all the power supply lines 3.3V, 2.5V and 1V. Power supply is stable, no sagging or noise.

3) How is the reset & power sequencing at room temperature ? At the higher temps ?
We have monitored the reset and power lines with the oscilloscope and have not been able to fault it.

4) What caps are used in this design ? dielectric = x5r ? If X5r, shift to X7r and test again. Avoid electrolytics and tantalums - consider ceramics wherever possible.
All caps are ceramic rated at 25V X7r.

5) Can you post your power supply and power sequencing circuit for a review ?
The issue arises when the Xmos has successfully powered on and is simply reset. How can the power sequencing be in question in this case?

6) Trusting the PCB assembly to be sound ?
We have over ten units made, assembled by machine all reproducing the same issue. We have checked and resoldered the Xmos ICs.


- Are !RST and !TRST being held low for long enough?
Held low for 10ms

- Are the reset lines being pulled right down to GND, or are they not getting quite low enough?
Pulled directly to ground.

- Is the power supply sequencing still within the timing spec at higher temperatures?
The issue arises when the Xmos is simply reset. The Xmos has already successfully powered on before reset. How is the power sequencing relevant in this case?

Thanks,
Daniel
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mon2
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Postby mon2 » Thu Dec 22, 2016 1:48 am

How are you performing a RESET on the XMOS device ? If a simple pushbutton (PB) switch then this can be an issue if the same PB is not debounced. All mechanical switches will generate signal bounce / ringing on the RESET line. Please confirm the details of the RESET action.

There are many small footprint ICs that will debounce the mechanical pushbutton to generate a perfect text book single square wave output.
plex
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Postby plex » Thu Dec 22, 2016 7:34 am

I have had a case where a clean power up would work but a reset would not. The reason was that the sequencing of the power supplies was not correct due to residual voltage in the 3v3 rail that would make the 3v3 regulator not start correctly.
Is the reset circuit tied to the power sequencing? For example in the x200explorer design the reset button also forces a reset of the 1v0 regulator. This is not required I think but make sure that the 3v3 and 1v0 rails behave according to spec.
henk
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Postby henk » Thu Dec 22, 2016 9:06 am

Hi Daniel,

By the looks of it, the second node is set to boot from any of links 4..7 (they have all been opened up); but only one of them seems to be connected. What signals are the other three links (XL5, XL6, and XL7) connected to?

On the off chance that they are connected to GPIO - spurious input on the RX lines may cause trouble (in particular a clock on i0); and the TX lines will be driven low, which could be a problem if the IO device is driving them high.

Cheers,
Henk
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Postby CrAzIaNhAx » Mon Jan 09, 2017 1:43 am

Hi All! I have been away for the Christmas/New Year Holiday. Thank you for your replies.

mon2
We are currently driving the reset line with a watchdog IC. We do not believe debouncing is the issue.

plex
Our issue occurs on both reset and clean power up after the Xmos has been running for a period of time. We have observed the power lines in both cases. On the clean power up the voltage lines are all fully discharged and the sequencing meets the specifications in the datasheet. The schematic is based off the xCore200 MC Audio Platform. There is a ADM1085 monitoring the 1V line in the reset circuit. Why would the power sequencing need to be redone on a reset?

Henk
We are using the XE216-512-TQ128 IC so the only links available are XL4 & XL7. All the RX of XL7 is NC, there is one TX used as a button input that is pulled high. If uninitialised are the XL7 RX pins floating? The data sheet specifies internal pullup/pulldown current at 100uA. During startup/reset would the internal weak pull downs be enough when the board is at higher temperatures? Attached is a screenshot of the schematic.
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mon2
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Postby mon2 » Mon Jan 09, 2017 5:46 am

The posted schematic does not offer details on how you are resetting this circuit nor the power supply sequencing. Please post the relevant details. Also be sure that the R19 is a 4R7 resistor (appears to be in the schematic with a value of 4.7R but confirm it is NOT 4.7k).

The ADM1085 is an open drain output so respectively, is there a pull-up at the output of this supervisor IC on your design ?

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