Synchronising multiple XMOS microprocessors Topic is solved

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
dsdanielko
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Synchronising multiple XMOS microprocessors

Postby dsdanielko » Thu Jun 09, 2016 1:55 am

Sorry if I am spamming the boards too much.

I have an external clock which is being fed into 1 bit ports of 16 microprocessors. Using this external clock, I am doing clocked I/O operations on every microprocessor. However, from my understanding, this does not actually mean that all 16 microprocessors I/O at the exact same time since the sampling and outputting happens on the edges of the 100MHz reference clocks in each microprocessor (which may be slightly out of phase between microprocessors) instead of the external clock.

Is my suspicion correct? And how do I fix this undesired behavior? I would like the microprocessors to I/O at exactly the same time.

Thanks
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henk
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Postby henk » Thu Jun 09, 2016 9:58 am

Hi dsdanielko,

I think they are synchronised to the 500 MHz core-clock; which is different on each processor.

When you say
I would like the microprocessors to I/O at exactly the same time.
You have to specify what this means. How much skew is allowed?
There is always going to be some skew.

Second question; are you trying to output the data on the clock-edge, or is the data output on various times related to the clock edge? Ie, is it like Data0 that you try and align with the clock edge, or like Data1 where you have known times between the clock edge and data edge(s).

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              ____________________
Clock _______/

      _______ ____________________
Data0 _______X____________________

      __________ ______ ________ _
Data1 __________X______X________X_
Cheers,
Henk
dsdanielko
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Joined: Sat Mar 12, 2016 3:12 pm

Postby dsdanielko » Thu Jun 09, 2016 10:06 am

Its like data 0 I believe since I am using the method from this example https://www.xmos.com/published/xc-clock ... and-output. The skew can be in the range of hundreds of nanoseconds or lower.

Also I have some 4 bit ports as well now and want them to perform outputs at the same time too.
henk
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Joined: Wed Jan 27, 2016 5:21 pm

Postby henk » Thu Jun 09, 2016 10:53 am

Hi,

The difference between Data0 and Data1 (both of which can be achieved with XC) is that if there is a delay between clock and signal, of say 1 ms, then this will introduce an uncertainty of something like 50 ns (50 ppm) due to differences between crystals. If there is no delay (Data0), then this uncertainty won't be introduced.

Say you use Data0. From memory, for this particular setup (outputting data on an external clock), you are looking at the data appearing 11-21 ns after the clock edge; which should be well within your spec of 100 ns. A small part of the uncertainty (2ns) is due to the external application-clock being resynchronised to the 500 MHz core-clock. The rest of this uncertainty is due to Process/Voltage/Temperature variations, which you could improve by keeping all chips at the same temperature, and giving them the same supply voltage.

A document explaining this for XCORE200 is in the pipeline.

To get multiple ports to output data make sure they are buffered

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buffered out port p:4 = XS1_PORT_4C;
buffered out port q:1 = XS1_PORT_1P;
And then execute all the outputs before the clock edge:

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p <: data;
q <: dataq;
... ; // lots of more outputs to different ports.
This will put each port in a position where it is waiting for the clock edge, and when it arrives they will all fire simultaneously. You can put these in a loop, as the first output will block when all buffers are full, waiting for all of them to go.

You have to be slightly careful about startup, and make sure that all cores are ready and waiting for the first clock edge before producing the first edge. After that they will all stay in sync.

Hope this helps,
Henk
dsdanielko
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Posts: 33
Joined: Sat Mar 12, 2016 3:12 pm

Postby dsdanielko » Thu Jun 09, 2016 11:11 am

Oh sorry I didn't mean 100ns I meant in the 100ps range. But as long as the clock edge to output delay is constant from microprocessor to microprocessor it shouldn't matter.

So there is no way to actually synchronise all the microprocessors' 500MHz core clocks to be exactly the same? I was thinking of maybe linking all the microprocessors' core clocks together or something.

Thanks for all the help so far
henk
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Posts: 346
Joined: Wed Jan 27, 2016 5:21 pm

Postby henk » Thu Jun 09, 2016 11:24 am

Hi,

100 ps is not very much is it? You will not be able to achieve anything close to that with an xCORE. Your best bet is an external flop; in each output signal, close to where you need the signal; that achieves a resynchronisation back to the external clock, leaving you only with variation in the clock and clock-to-data times of the flop.

You may be able to achieve some sort of synchronisation of the 500 MHz clocks, by running them all of a single oscillator. If you pick the right input oscillator and the right PLL settings, you may get some phase lock between the oscillator edge and core-clock edge. There is hopefully somebody on the forums who knows about these things.

I am sure you have worked this out, but every inch of PCB trace adds 100 ps delay to your signal, so your clock distribution has to be spectacularly precise!

Cheers,
Henk

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