XHRA-2HPA MCLK Options Topic is solved

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
DHembree
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Joined: Fri Apr 15, 2016 6:46 pm

XHRA-2HPA MCLK Options

Postby DHembree » Mon Apr 25, 2016 9:10 pm

I am working on a project using the XHRA-2HPA as a USB-I2S bridge. I am intending, at least initially, to configure the device using straps. According to the device data sheet there are two sets of sample rates available by selecting one of two MCLK clock rates (24.576 and 24.5792MHz). Are there any preferred methods for selecting MCLK signals? I am assuming I will need two clock circuits - one for each MCLK signal. I2C interfaces are not an option as the system is in parallel (strap) mode.

Thanks in advance,
Dan
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Ross
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Postby Ross » Mon Apr 25, 2016 10:47 pm

A couple of options spring to mind, using a phaselink part (as on a most recent XMOS boards) or using a circuit like that on the original L-series based USB audio board, from the HW manual:
Two crystal oscillators are used on the board to support the two standard sample rate base frequencies (44.1 and 48kHz). The crystal oscillators are built using discrete components for low cost and easy availability however standard canned oscillators could also be used. The oscillator design is a simple Pierce oscillator using an unbuffered inverter as the amplifying component. The MCLK_SEL signal selects which of the two oscillators is enabled, only one is enabled at any one time to avoid any interference from the unused clock.
Full details details here:
https://www.xmos.com/support/boards?product=14772
DHembree
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Posts: 75
Joined: Fri Apr 15, 2016 6:46 pm

Postby DHembree » Wed Apr 27, 2016 8:44 pm

Once again, thank you!

Dan

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