Buffers for TRST_N and RST_N. Topic is solved

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
y0lo
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Buffers for TRST_N and RST_N.

Postby y0lo » Tue Apr 05, 2016 7:39 am

Hi,

Almost all XMOS reference schematics suggest to use buffer between supervisor and RST_N / TRST_N.

Is it necessary to use the buffer?
Can I connect RST_N without buffer and leave TRST_N float (there is internal pull up)?
Could it cause any problems?

Best regards,
Ivan
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Ross
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Postby Ross » Tue Apr 05, 2016 11:30 am

Which device are you using?
y0lo
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Postby y0lo » Tue Apr 05, 2016 2:29 pm

I use XS1-L6A.
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Ross
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Postby Ross » Tue Apr 05, 2016 3:03 pm

From the data sheet:

Section 9: JTAG
The TRST_N pin must be asserted low during and after power up for 100 ns. If JTAG is not required, the TRST_N pin can be tied to ground to hold the JTAG module in reset.
Appendix F: Device Errata
To guarantee a logic low is seen on the pins RST_N, MODE[3:0], TRST_N, TMS, TCK and TDI, the driving circuit should present an impedance of less than 100 Ω to ground. Usually this is not a problem for CMOS drivers driving single inputs. If one or more of these inputs are placed in parallel, however, additional logic buffers may be required to guarantee correct operation.
For static inputs tied high or low, the relevant input pin should be tied directly to GND or VDDIO.
Appendix H: Schematics Design Check List
The RST_N and TRST_N pins are asserted (low) during or after power up. The device is not used until these resets have taken place.
As the errata in the datasheets show, the internal pull-ups on these two pins can occasionally provide stronger than normal pull-up currents. For this reason, an RC type reset circuit is discouraged as behavior would be unpredictable. A voltage supervisor type reset device is recommended to guarantee a good reset. This also has the benefit of resetting the system should the relevant supply go out of specification.

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