Static routing on XS2 Topic is solved

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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data
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Static routing on XS2

Postby data » Wed Mar 23, 2016 3:24 am

This is a question about how static routing works on the XS2, as opposed to the XS1.

In the switches on both the XS1 and XS2 parts, for each link there is a static link configuration register which determines the chanend to which data arriving on that link will be sent. The chanend is identified by a number from 0..31; the field is five bits wide.

On the XS1-L parts, there seems to generally be one switch per tile. There are 32 possible chanends, and five bits to identify one of them. No problem here.

On the XS2 parts, there is one switch for two tiles, and the switch register layout looks the same as XS1 -- the channel number field in the static link configuration registers is still five bits wide. However, since this one switch deals with two tiles, it has 64 chanends to choose from.

My question is: on the XS2, with only five bits per channel field in the switch, but 64 possible chanends, how does the switch determine to which chanend to send data arriving on a static link?
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henk
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Postby henk » Wed Mar 23, 2016 1:42 pm

Hi data;

There are indeed 64 channel ends; 32 per tile

Use bit 8 in the register, set it to 0 to go to tole 0, and 1 for tile 1.

Cheers
Henk
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data
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Postby data » Wed Mar 23, 2016 1:42 pm

henk wrote:Hi data;

There are indeed 64 channel ends; 32 per tile

Use bit 8 in the register, set it to 0 to go to tole 0, and 1 for tile 1.

Cheers
Henk
This solved my problem! It seems to be working now. Thank you very much!

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