Migrating from XS1 to XS2

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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gerrykurz
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Migrating from XS1 to XS2

Postby gerrykurz » Mon Mar 14, 2016 1:41 am

I have a design using two XS1-L16A-128-QF124 parts. I am looking to migrate the design to XS2 parts.

When I compare the XS1-L16A-128 to the XL216-512, I have the following questions:

XS2 has 8 xConnect links bonded out, XS1 has four bonded out and four internal.
How many internal xConnect links does the XS2 have?

The XS1 has 64 channel ends, 32 for each tile but the XS2 has only 32.
Is this true? It seems to be a serious reduction of capability.

In the XS2 flash versions, can the flash memory be programmed from an external processor using the Tile 0 ports or can it only be programmed using xFlash?

Can one XS2 boot via internal flash and the second one boot from xConnect?

Are all the XL and XE variants currently available, the flash and non-flash version, the 256K and 512K versions, the industrial and commercial temperature versions?

Any help with these questions would be appreciated as I need to make a decision of which way to go fairly quickly.

Thanks,
Gerry
henk
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Postby henk » Mon Mar 14, 2016 12:19 pm

Hi Gerry,

The XL216-TQ128 is more or less the equivalent of the XS1-L16-QF124; but not completely (different link configuration as you spotted), the XL232-FB374 (?) is more or less the equivalent of two XS1-L16-QF124 sitting side by side; but possibly fewer ports; depending on what you use. Replace XL with XU if you use USB

> XS2 has 8 xConnect links bonded out, XS1 has four bonded out and four internal.
> How many internal xConnect links does the XS2 have?

The XS2 chip has no internal links - it has a single crossbar that connects both tiles. As such, the single crossbar has 8 external links that you can use to connect it to other XS2 chips

> The XS1 has 64 channel ends, 32 for each tile but the XS2 has only 32.
> Is this true? It seems to be a serious reduction of capability.
They all have 32 channel ends per tile; please let us know which document says it has 32 and we will fix it.

> In the XS2 flash versions, can the flash memory be programmed from an external processor using the > Tile 0 ports or can it only be programmed using xFlash?
Both. QSPI flash comes out on 6 pins (the data sheet says which ones exactly), and you can program it over those pins. Note that you need to be careful that if you put a PCB trace on the clock you need to terminate it to stop reflections into the package. See the data sheet.

> Can one XS2 boot via internal flash and the second one boot from xConnect?
Yes. Or three from xCONNECT and one from flash. Using a single flash is the configuration that the tools support by default

> Are all the XL and XE variants currently available, the flash and non-flash version, the 256K and 512K > versions, the industrial and commercial temperature versions?
I am pretty sure they are.

Hope this helps,
Henk
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Postby henk » Mon Mar 14, 2016 12:59 pm

Just realised that the wording of the "Internal links" may be ambiguous.

The XS1-L16 has four internal links that connect the two XS1-L8 together, without taking up any GPIO

The XL216 has no such links to the outside world - all its links are overlaid on GPIO. So if you connect two XL216 together, you will take out some GPIO. Having said that, four of the links are overlaid on th slow bits of port 32; these can be used with little impact.

Two questions to help you with your migration:

1) How many two/five wire links did you use to connect your two XS1-L16 together?

2) How many (and which) GPIO did you use between the two XS1-L16s?
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gerrykurz
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Postby gerrykurz » Mon Mar 14, 2016 8:00 pm

Hi Henk,

Thanks for your response.

Right now, I have one 5 wire link connecting two XS1's and I want to increase this to two. This is a bit challenging from a PCB layout perspective using the XS1's. The XS2's have a much better pinout for connecting two parts together but as you have pointed out, it takes up IO that I am currently using so I would have to reassign these in the layout. This is doable but awkward in the TQ package, so I am evaluating the trade-off. However, since the XS2 parts are cheaper, faster, and have more memory I would like to migrate to them now.

Regarding the internal links, the XS1 has four internal xConnect channels connecting the two tiles.
Are you saying that the XS2 does not have this limitation? In other words, is it effectively a single 16 core device? If not, how do the two internal cores communicate? Is there a document that describes the new XS2 xConnect architecture in more detail?

Regarding the channel ends, in all the data sheets for the XS2 that I have downloaded, in Section 2 Features it states that there are 32 channel ends. In the XS1 datasheets, in the same section, it states there are 64 channel ends. This is confusing when trying to compare the two parts.

When you say that a single flash is supported by default for multiple devices, does this mean I could not use two devices each with their own flash?

Thanks again,

Gerry
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Postby henk » Mon Mar 14, 2016 9:46 pm

Hi Gerry,
Right now, I have one 5 wire link connecting two XS1's and I want to increase this to two. This is a bit challenging from a PCB layout perspective using the XS1's. The XS2's have a much better pinout for connecting two parts together but as you have pointed out, it takes up IO that I am currently using so I would have to reassign these in the layout. This is doable but awkward in the TQ package, so I am evaluating the trade-off. However, since the XS2 parts are cheaper, faster, and have more memory I would like to migrate to them now
You have three options here:
1) Use two XL216-TQ128. Connect them using 7<->0 and 4<->3; the downside is that you will knock out 40 IO pins, including 8-bit and 1-bit ports.
2) Use two XL216-FB236. Connect them using 6<->1 and 5<->2; the downside is that you will need HDI PCBs
3) Use one XL232-FB374. This has all four links wired up. Downside is that 40 IO pins have been knocked out, like (1), and you may need a few extra layers in your PCB.
Regarding the internal links, the XS1 has four internal xConnect channels connecting the two tiles. Are you saying that the XS2 does not have this limitation? In other words, is it effectively a single 16 core device? If not, how do the two internal cores communicate? Is there a document that describes the new XS2 xConnect architecture in more detail?
Not really a single 16-logical-core device; there are still two tiles, but they connect to the same xCONNECT switch. In the XS1-L16 each tile has its own switch; but in the XL216 there is one switch that wires up to both tiles. The XS2 xCONNECT switch is just like the XS1 xCONNECT switch but both tiles have four parallel links into a crossbar switch, with eight links going out to the world. Compare Figure 1 of the latest version of the XL216 with Figure 1 of the XS1-L16 and you will see the difference

At present there is no separate document, but we shall soon release the xCORE200 xCONNECT document.
Regarding the channel ends, in all the data sheets for the XS2 that I have downloaded, in Section 2 Features it states that there are 32 channel ends. In the XS1 datasheets, in the same section, it states there are 64 channel ends. This is confusing when trying to compare the two parts. The picture on page
Thanks - this will be fixed.
When you say that a single flash is supported by default for multiple devices, does this mean I could not use two devices each with their own flash?
You can connect a flash to each device, but I don't know whether you can use multiple flash to boot a single system. Tile 1 can only boot through the xCONNECT from flash on Tile 0. I don't know whether you could connect a flash to both Tiles 0 and 2 and boot 1 from 0 and 3 from 2...

Cheers,
Henk
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Postby gerrykurz » Wed Mar 16, 2016 4:26 am

Another difference I noticed on the XS2 in the TQ128 packages is that the DEBUG pin is not bonded out.

What is this pin used for?

In the XS1 datasheet, it is described as a multi-chip debug I/O line. Is it required for multi-chip designs?
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gerrykurz
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Postby gerrykurz » Wed Mar 16, 2016 6:47 am

Another thing I noticed is that the XS2 does not boot from JTAG.

Does this mean you have to reprogram the flash each time you make a code change?

Also, when booting from Channel end 0 Mode 111 are both links enabled by default (XL0 and XL3) or can just one of them be used?

How does boot mode 011 work?
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Postby henk » Wed Mar 16, 2016 9:37 am

Hi Gerry,
Another difference I noticed on the XS2 in the TQ128 packages is that the DEBUG pin is not bonded out.
That's correct - the TQ128 package is optimised for IO; not for multi-chip. In a multi-chip design, when one chip enters DEBUG mode it will take a little while for other tiles to enter DEBUG mode, meaning that the program you look at will have some threads slightly further advanced than others.

If you want to stop all threads at the same time, you can tie all DEBUG_N pins together. When configured to react to pins, all tiles can stop more or less simultaneously when one stops. See Section 10 of the data sheet of the FB236 package for more information.
Another thing I noticed is that the XS2 does not boot from JTAG.
It can and does boot from JTAG - but it uses a different mechanism. Rather than having an external line to pull it low, it is set to boot from JTAG through the JTAG chain itself. The debugger can also issue a reset through the JTAG chain and set the PLL; all in one operation. This reduces design complexity.
Also, when booting from Channel end 0 Mode 111 are both links enabled by default (XL0 and XL3) or can just one of them be used?
There are four modes to boot from Channel end 0. Mode 111 enables four links XL0..XL3, so it can boot over any of those. If there are IO devices clocking away on, for example, XL3 this could cause trouble. If you just want to use one of them, use Mode 100. That only enables link XL0.
How does boot mode 011 work?
Section 8.3 of the datasheet shows that. You can use it to boot the device from an external processor that supports SPI master.

Cheers,
Henk
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gerrykurz
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Postby gerrykurz » Thu Mar 17, 2016 7:47 am

Thanks for the response.

I understand that Tile 0 boots from an SPI master in modes 010 and 011.

What is not clear is how Tile 1 boots from the SPI master in mode 011 as it does not have access to the Tile 0 SPI port. Does Tile 1 implement a second SPI slave port in mode 011? If so, what pins does it use? X1D00, X1D10 and X1D11? This is not at all clear in the datasheet.
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Postby henk » Thu Mar 17, 2016 8:08 pm

I understand that Tile 0 boots from an SPI master in modes 010 and 011.

What is not clear is how Tile 1 boots from the SPI master in mode 011 as it does not have access to the Tile 0 SPI port. Does Tile 1 implement a second SPI slave port in mode 011? If so, what pins does it use? X1D00, X1D10 and X1D11? This is not at all clear in the datasheet.
Aha I see.

Yes, it does use X1D00, X1D10, and X1D11. Just a word of caution, like booting from separate flash, I don't know whether that mode is supported by the tools. Mode 010 allows all to be booted through Tile 0, which is the default model that the tools use.

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