About multicore function of the microcontrollers

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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kreni
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Posts: 2
Joined: Wed Jun 24, 2015 10:50 am

About multicore function of the microcontrollers

Post by kreni »

Hi!

I am a student, and I want to learn more about the features of multicore microcontrollers.

Does any detailed documentation exist (preferably published by XMOS), where I can learn about them? I saw some books on the internet, but I am not sure, that in these books, the multicore microcontrollers architectures functionality is the same, as in the xCORE microcontrollers.


Another question:

I am working with a CAN gateway with two(!) XS1-L8A-64-LQ64 microcontrollers, each with 1-1 Tile.
I want to make my program to do so: The specified parts of the program should run on different cores and Tiles.

For example: This code part runs now on the same Tile:
int main()
{
streaming chan c_can1;
streaming chan c_can2;

par
{
on tile[1]: application(c_can1, c_can2, 10000000, 0x12345678);
on tile[1]: can_server(c_can1, p_can1, t_can1, CAN_BUFFER_SIZE);
on tile[1]: can_server(c_can2, p_can2, t_can2, CAN_BUFFER_SIZE);
}
return 0;
}

But when is try to run them on different Tiles, or on the same Tile, but on a specifield core, than it does not work. (BTW. How should I number the Tiles, when they are on a different microconroller? Makes the xTIME Composer Studio the connection automatically?)
Is it possible somehow, to solve the problem?

Thank you for your answer.


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myndideal
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Posts: 59
Joined: Thu May 05, 2011 10:00 pm
Location: Budapest

Post by myndideal »

Hi,
obviously the two can_server() function must be on the original tile, because these are use the p_canX port refs. This part of the code is depends on the hw design. The application() function probably can be movable to tile[0] if you want. Because this one parametrised by only channel resources. In this case c_can1, c_can2 will be routed trough the xlink between the two of the xmos chips.
In my opinion, specification of the exact core isn't necessary.
The original version will starts running on the tile[1].core[0] 'til the par{} block, then small schedular code forks, which starts the par statements on different cores.
When the application() block assigned to tile[0], therefore we are using two tiles really. In this case there will be two relevant start processes, where we can takes care. On the tile[0] the application() will be started, on its core[0]. Meanwhile the tile[1] will be organised similar way like before, but application() will be not compiled there at all, beacuse it is assigned/compiled already on another tile.
The actual communication works on the same xlink switch inside your #1 chip, but in the second case the communications will be sent to outside between #0 and #1 tiles (which are located in different chips).

So, unfortunately moving the can_server() function to other tile is not possible, if theres no can pin in your board designed. I assumed, to have the releavant pins conneted only to second chip.
Btw, if #0 chip has similar can ports too, obviously you can define here a new can_server() entry point too for this another pins... This kind of hw pin related functions must be run on the tile, where the pins are...

Numbering of the tiles is depending on xn file. In case of multiple tiles, ther is a node refference number, or something like this... Compiler generates a platform.h temporary file, which contains this kind of informations, based on xn file specifications.