Misc. XS1-U8A connectivity questions

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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jjlm98
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Misc. XS1-U8A connectivity questions

Postby jjlm98 » Thu Sep 04, 2014 3:02 pm

Hi folks, just a couple questions regarding this device:

1) Page 28 of the data sheet states that "The AVDD decoupler and wiring can be removed if
the ADC is not used." - can I assume this means to FLOAT this supply pin as opposed to terminating in some way? Can the four ADC inputs be FLOATed as well, without the need for any sort of termination?

2) Apologies if this was made clear somewhere else - but can anyone clarify this warning on page 99 of the data sheet under the schematic checklist: "You have not mapped both inputs and outputs to the same multi-bit port." What delineates a multi-bit port?

Thanks in advance!
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Bianco
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Postby Bianco » Thu Sep 04, 2014 5:48 pm

jjlm98 wrote:
2) Apologies if this was made clear somewhere else - but can anyone clarify this warning on page 99 of the data sheet under the schematic checklist: "You have not mapped both inputs and outputs to the same multi-bit port." What delineates a multi-bit port?

Thanks in advance!
A multibit port is any port with a width larger than 1, examples: XS1_PORT_4A, XS1_PORT_8A, XS1_PORT_16A, XS1_PORT_32A.
All the bits in a port have the same direction, either input or output. It is possible to change the direction at run time but this again will change the direction of all bits in the port. Something to keep in mind if you use some bits of the port as input and others as output.
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larry
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Postby larry » Thu Sep 04, 2014 6:17 pm

I remember a guideline that said that floating pins can increase EMI emissions and should be tied to ground.
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jjlm98
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Postby jjlm98 » Thu Sep 04, 2014 8:09 pm

Thanks guys! Just a couple follow-up questions:

Bianco - I have a better understanding of this now after paying closer attention to section 7.3 in the data sheet ("Ports and Clock Blocks.") Are there any restrictions with signals in a multi-bit port, relative to physical GPIO location? Specifically, I am in the process of pinning out the GPIO of the device, and I'm trying to understand if there are restrictions in how the signals are physically grouped (for example, if one physical pin is intended as an output, does that force implications on neighboring pins, etc)? Or is the port-to-GPIO mapping completely configurable in firmware?

larry - can you point me to the source of this guideline (application note, etc)? While I share your experience with this concern, I would have expected that recommendation to have been called out explicitly if it were the case here. However, the dashed box labelled "only required if ADC is used") in Figure 22 of the data sheet implies to me that the connections can be removed completely.

Cheers.
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Bianco
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Postby Bianco » Fri Sep 05, 2014 8:23 am

Ports of different widths can overlap and be multiplexed to the same physical pins.
You can see this in any device datasheet in the port map table.
Which ports are active is defined in software.
If overlapping ports are active, the smallest port takes precedence.
Say a 4 bit port and a 1 bit port are overlapping. If they are both active, the 1 bit port takes precedence and the 4 bit port will only manage the remaining 3 physical pins.

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