XS1 GPIO output stage

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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XS1 GPIO output stage

Postby pasau » Fri Aug 22, 2014 1:22 am

Hi, i would like to know what the output/input stage looks like for ports on xmos chips (open-drain, push-pull, etc.). The datasheet only says there is a 35k pull-down resistor, but not very specific on how the data is driven on pins. Since there is already a pull-down i would maybe think there is an open-drain configuration for driving the high level, but really i just dont know. Is there an explanation and schematics of XS1 ports at transistor level? Most stuff seems to cover only how to interact with port registers from programmatic view.

I need a better understanding of this since i want to interface with some 1.2 V logic by using a voltage shifter.

Thank you!
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Postby mon2 » Fri Aug 22, 2014 3:41 am

Is your 1.2 volt interface bidirectional or unidirectional (read or write) ?

If you will be writing to the external logic then it is very possible and common that the logic device is 3.3 volt tolerant. That is, you will still power the external device at 1.2 volts but the device is capable of allowing for a 3.3 volt input logic level. The datasheet should offer such details.

Otherwise, can you share more info on the external device you wish to interface ?

How many bits ?

At what speed would you like to operate this external 1.2 volt logic ?
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Postby segher » Fri Aug 22, 2014 6:23 am

You can use set_port_drive_low() on 1-bit ports to switch
the port to O/D output. You'll need an external pullup.

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