Question about event/interrupt management for multiprocessor

[cpapadopoulos]

Hello,

I am trying to create an intelligent controller that distributes interrupts/threads between processors of a 2 processor system. The controller could be implemented in hardware or combination hardware/software.

I would like to ask how do you distribute interrupts/threads between your multiprocessors? Also how do you deal with possible dependencies between interrupts/threads?

Thank you
Haris

[sethu_jangala]

You can do that using channels in xCORE. You can use channels and select statement to notify events.
More information on Channels and select statements are available in xC programming manual.
https://www.xmos.com/support/documentat ... nent=14806

Sethu.

[cpapadopoulos]

Thank you for the reply. I see only c code in this documentation while I need to implement this mechanism in hardware (vhdl). Is there any documentation about how these channels are implemented in hardware?

Thanks again

[sethu_jangala]

I see only c code in this documentation while I need to implement this mechanism in hardware (vhdl)

You mean assembly way of implementation? You can find the architecture manual in the following link:
https://www.xmos.com/en/download/public ... 79A%29.pdf

[cpapadopoulos]

Hello,

thanks for the reply.

No I do not mean assembly code. I need a hardware RTL implementation of this mechanism (the channels mechanism). I do not know if you can share this.

Thanks

[Folknology]

If you mean XC for HDL folk then this might help : http://www.slideshare.net/xmos/xc-progr ... -designers

and http://www.slideshare.net/xmos/xmos-vs-fpga

Or if your interested in implementing Xmos link technology in FPGAs then these links migth help:

https://github.com/BiancoZandbergen/XMOS_Optopus1 (@bianco)


And some link background https://www.xmos.com/en/published/xs1l_links?secure=1

Also be aware that G and L versions of the links are not compatible.

Hope this helps

regards
Al