I've seen discussions about SPI pin reuse and references to documentation. However, reading the documentation I do not see a clear indication that the SPI pins are released for general I/O after a boot sequence.
If I set MODE[3:2] to "11" binary - boot from SPI - then after the boot process is complete - are SPI released for general I/O?
My current assumption is that firmware need not make any special consideration for reuse of the SPI pins since once firmware is running - the SPI boot is already complete and pins are released (mux is switched) for GPIO use.
My question is only on the XMOS behavior as implications outside of XMOS are already understood.
Regards,
Jason Whiteman
SPI Pins Available After Boot - Confirmation?
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JasonWhiteman
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segher
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The ports are disabled after loading the boot image.
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Ross
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You can declare and use them as normal ports in your program (the boot code uses these pins via normal ports).
Clock and data lines can simply be re-used, some sort of mux should be used if you want to re-use the Chip Select line.
Clock and data lines can simply be re-used, some sort of mux should be used if you want to re-use the Chip Select line.
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JasonWhiteman
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Muxing CS# is more of an external consideration as the system needs to protect the SPI part from getting confused if CS# is asserted -- so there's no special XMOS-driven consideration for CS#.
The plan was not to reuse CS# and, in the code, drive CS# high (the GPIO) to double ensure CS# is not asserted.
Conclusion (correct?):
Even though the MODE pins are configured to SPI boot mode (11), all SPI pins (X0D00, X0D01, X0D10, X0D11) are available for use for thread(s) without any special code.
Regards,
Jason Whiteman
The plan was not to reuse CS# and, in the code, drive CS# high (the GPIO) to double ensure CS# is not asserted.
Conclusion (correct?):
Even though the MODE pins are configured to SPI boot mode (11), all SPI pins (X0D00, X0D01, X0D10, X0D11) are available for use for thread(s) without any special code.
Regards,
Jason Whiteman
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Ross
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- Location: Bristol, UK
CorrectJasonWhiteman wrote:Muxing CS# is more of an external consideration as the system needs to protect the SPI part from getting confused if CS# is asserted -- so there's no special XMOS-driven consideration for CS#.
Sounds good to me.JasonWhiteman wrote: The plan was not to reuse CS# and, in the code, drive CS# high (the GPIO) to double ensure CS# is not asserted.
CorrectJasonWhiteman wrote: Conclusion (correct?):
Even though the MODE pins are configured to SPI boot mode (11), all SPI pins (X0D00, X0D01, X0D10, X0D11) are available for use for thread(s) without any special code.