Sample! Sample! Sample!

[SpacedCowboy]

I'm wondering whether an Xmos chip can do the job of an FPGA that I have in a project I'm working on. The main issue is that I have an incoming data signal (lvds, but I can cope with that and turn it into ttl) which is at one of several frequencies with the highest being ~20 MHz.

Since I don't know the incoming frequency, I'm treating it like an uart, and oversampling to recover the clock rate and the data. The FPGA is doing this at just under 1GHz, but I don't think that's necessary, I've seen some code/posts on this forum about generating a 200 MHz clock by changing the reference clock, and if I can sample at that speed too, I think it'd be fine. I also have to send data back at one of two clock rates, but those are both under 20 MHz, so I don't think that's a problem, it's the recovery that's hard. So is this a reasonable thing to try ?

The data is also encoded in 8b10b, and I was wondering if the serdes options for port I/O allowed odd serialization values like 10 bits ? Or do you have to stick to 4,32 ? It's not the end of the world if it can't, I'll just operate on packets of data 160 bits long, receiving them 32 bits at a time.

Cheers
Simon

[stefanharjes]

Hi,

I am very confident that 50 MHz (66 on a 125MHz chip) is the max you can achieve. Buffered io's are very nice, but I have not found a way to do sizes between 8/16/32.

Best
Stefan

[Lele]

Tere are partin and partout instruction to do partial input/output of any odd number of bit. Also there is instruction to dalay input sampling instant in steps of system frequency (2.5ns for 400Mhz parts). I never used this option but, for example, one could connect the same signal to a couple of input pin, delay the second one by half sampling period and then interleave the two streams thus doubling the sampling freq...
However I remember that there is a phisical limit of 60Mhz for the pin; don't know if it is still there for the new parts.

[Lele]

To get the frequency of the signal you could use transition event and timestamp instead (just a select with pinsneq instruction)

[Bob]

Thank you for those pieces of info Lele. Can see plenty of uses for both, in instrumentation and control applications. Having detail vernier control over both frequency and phase allows matching of external resonant systems, detail synthesis of dither, generation of subharmonics etc.

[JasonWhiteman]

FMax for port I/O is documented in the part's datasheet and further port I/O timing information is contained in document X5821.

As I am using the Slicekit, which has an XS1L16A, the links are currently (and subject to change):

I/O Timings:
https://www.xmos.com/en/download/public ... 21A%29.pdf

Datasheet (one example, sku in slicekit)
https://www.xmos.com/en/download/public ... 06E%29.pdf

Page 4 features mention Fmax, page 24 defines Fmax as part of the AC characteristics.

Additional information:
https://www.xmos.com/download/public/XS ... .02%29.pdf


Regards,
Jason Whiteman