Power On Reset - MultiChip ?

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
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lilltroll
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Power On Reset - MultiChip ?

Post by lilltroll »

I have a problem with Power On Reset on a custom made board.

I have 3 L1; each with its own power-supply and POR cuircuit but only one FLASH for boot. The 2 slaves shall boot via XLINK.
It works fine with the XTAG2 not using the flash, with the JTAG chain connecting them together.
It is possible to flash the card without any error.

Powering it on without the XTAG´s will thus result in 3 different POR, but that doesn't work - the master will never start reading the flash.

Manually resetting all chips at the same time works fine, and all cores boots.

I found this topic
http://www.xcore.com/forum/viewtopic.php?p=13744#p13744

What is the timing requirement for the reset in a multi-chip setup with independent reset?

Why does the master never start reading the FLASH? If it was a problem with the XLINK timing, I suppose it should at least read the code first prior to a failure.

I can program the POR delay so it will be released in a specific order.
I have tested a POR-time of 1.7s on the master - it didn't work - but a manual reset still works. What is the difference ?


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lilltroll
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Posts: 956
Joined: Fri Dec 11, 2009 3:53 am
Location: Sweden, Eskilstuna

Post by lilltroll »

Reading the http://www.xmos.com/download/public/XS1 ... 51A%29.pdf

An example with a 2 chip configuration with the first chip master connected to a SPI-FLASH and the second chip slave boots from the master over XLNIK.

Is it the slaves that sends one "HELLO" message over the XLINK to the master - then the master sends back a CREDITX. ??

That would suggest that the release of the reset must happen first or at the same time on the master to ensure that the master is ready to receive the HELLO from the slave.
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