When you do a timed output the instruction doesn't wait for the output to happen, instead it sets some state in the port to ensure that the specified value is output at the specified time in the future and returns. This explains why a short period of time is measured between c1 and c2.
The port is only able to buffer a single timed output in the future. If you do a timed output and there is already a pending timed output the instruction must pause until the first timed output has taken place before setting up the second timed output. This explains why the time between subsequent output instructions is longer.
To explain the difference between the (c3 - c2) and (c4 - c3) consider the times when the outputs will complete. We know the first output completes at count since we took a timestamp. The second output will complete at count + x (where x is the number of ticks needed to execute the instructions between the first and second output). The third output will pause until the second output has taken place, i.e. it will complete at count + 300. The fourth output will pause until the third output has taken place, i.e. it will complete at count + 600
Therefore we have:
From this point onwards the time elapsed between pairs of output instructions should be 300. The values measured using the timer may might be slightly off these expected values because the timer will be input from slightly after the output instruction actually completes.