Too fast for even XMOS :( reducing data frequency

[microfrustration]

Hey, nice to join this place!

Lets say I would like to slow down DVI signal (108 mhz clock) by a factor of 2, basicly elongate every signal variation by 2.

All logic, syncs, clock (obviously)...

Is there an IC that can do this, or I have a long FPGA puzzle ahead of me ?

I was wondering, what is the correct electronics term of ''elongating'' signal variation time by factors of 2/4/8 etc... I am looking for a fancy name.

Thx you.

[microfrustration]

I forgot to mention, yes this will be sampled not too often.

4-5 times a second, rest will all be discarded, this will not be viewed or watched or used.

[diltsman]

I assume that you need to slow it down so that you don't exceed the 100 MHz pin rate, right? Given that video signals tend to be continuous you would still have to process the data at the 110MHz rate or your signal (and associated buffer) will quickly get backed up.

[segher]

A DVI signal with a 108MHz clock has the data lanes going at 1.08GHz;
your problem is bigger than you think. Also there is the loveliness that
the clock is not aligned with the data at all.

What are you *actually* trying to do? Maybe you can get away with
using the sync signals, for example.

[Berni]

So you want to grab 1 frame from the video feed and retransmit it at half the speed? Because then you will need a large FIFO buffer than can store nearly the whole video frame inside of it. So that will most likely require an FPGA to do.