Hello guys, it's me again!
In the past few weeks i've spent a lot of time reading and learning about XMOS.
One question is still alive, that i cannot answer:
How is the memory access/management working on an XMOS? Is it Harvard/von Neumann or a mix? How are instructions/data loaded from it?
Obviously in basics it seems like a von-Neumann thing, because there's only one SRAM. But maybe its divided internally?
There so much information about channel communication, links and so on, but i didn't found any documentation about memory access, beside that every logical core has 16 32Bit Registers for instructions and that there is a little instruction fetching, because the most instructions are 16Bit.
I know, it's maybe a stupid question, but I really would enjoy it, if somebody have some hints for me, maybe i just didn't found the right documents?^^
Greetings
XMOS - Harvard/von Neumann?
Have a look at chapter 5, "Instruction Issue and Execution" in
"The XMOS XS1 Architecture". If you have any questions left
after that, ask away :-)
"The XMOS XS1 Architecture". If you have any questions left
after that, ask away :-)
Hmm well...actually i read that already but maybe i didnt spent enough attention on it :D
4 stage pipeline ... so instruction and operand fetching are made consecutively ... and that means von Neumann... right?^^
i dont like that sentences like "typically over 80%" and so on^^ i think i just have to trust, that the memory access is no bottleneck :)
Greetz
4 stage pipeline ... so instruction and operand fetching are made consecutively ... and that means von Neumann... right?^^
i dont like that sentences like "typically over 80%" and so on^^ i think i just have to trust, that the memory access is no bottleneck :)
Greetz
The instruction fetch is done at the end in the pipeline, (no instruction fetching is done if a load or store instruction accessing the SRAM was used).
The pipeline is very short, 64 bit's. An empty instruction cache will issue a FetchNoOperation FNOP. There is no (need for) branch-prediction since the next operation after a branch will be fetched as the last step in the pipeline for the branch instruction.
Thus, a program that uses many Store/Load from SRAM might have some FNOPs if the compiler cannot insert other instruction in between the Load/Store instructions, but the FNOPs will be deterministic. Since it is a RISC machine most often instruction that fetches instruction is needed anyway between LOAD/STORE.
Worst case is that 1 FNOP that must be inserted with the penalty of 1 clock-cycle, and there will never be a race between Load/Store SRAM acess vs. instruction fetch.
The pipeline is very short, 64 bit's. An empty instruction cache will issue a FetchNoOperation FNOP. There is no (need for) branch-prediction since the next operation after a branch will be fetched as the last step in the pipeline for the branch instruction.
Thus, a program that uses many Store/Load from SRAM might have some FNOPs if the compiler cannot insert other instruction in between the Load/Store instructions, but the FNOPs will be deterministic. Since it is a RISC machine most often instruction that fetches instruction is needed anyway between LOAD/STORE.
Worst case is that 1 FNOP that must be inserted with the penalty of 1 clock-cycle, and there will never be a race between Load/Store SRAM acess vs. instruction fetch.
Yep. To say things even simpler:
All instructions are issued from the instruction buffer, instruction
issue never causes fetches from memory.
At the end of execution for every instruction, if the instruction does
not access memory and there is space in the instruction buffer, an
instruction fetch is done.
All instructions are issued from the instruction buffer, instruction
issue never causes fetches from memory.
At the end of execution for every instruction, if the instruction does
not access memory and there is space in the instruction buffer, an
instruction fetch is done.
Ahhh i thank you very much!
Actually i should've understanded that by myself in the architecture pdf... maybe my english is too bad ;X
but i got it now, thanks to your explanations!
greetings
Actually i should've understanded that by myself in the architecture pdf... maybe my english is too bad ;X
but i got it now, thanks to your explanations!
greetings