Digital Down Converter

[ahenshaw]

That's fantastic! I'm going to play with this a bit and see what I can do with it. Thanks!!

[lilltroll]

That's fantastic! I'm going to play with this a bit and see what I can do with it. Thanks!!

This give you a hint of the form of the filter coefs:
MATLAB
[B,A]=butter(2,0.01);
int32(B*2^31);
int32(2^31*[-A(2)*0.5 -A(3)]);

(rounding may also be a good thing)

Also in the code b0=b2 to increase speed, but that is not a problem for LP filters (symmetry)

B =

1.0e-003 *

0.2414 0.4827 0.2414

>> A

A =

1.0000 -1.9556 0.9565

Becomes

b0=518315 b1=1036629 (b2=518315)

a1=2099786147 a2=-2054161904



||a1|| can become larger than one, and that is the reason for the shift instruction in the code

[lilltroll]

What about 200 kHz x4x8 = 6.4 MHz
or 200 kHz x6x6 = 7.2 MHz

6:th order LP filter in stage I downsampling 1:6 or 1:8 (3 threads + a decimation tread that sleeps most of the time)

> 6:th order in stage II that will have a much more step rolloff between the passband and the stopband, but will be using other filter code that fetch filtercoeffs from SRAM instead of registers, e.g. running several BiQuads per XMOS-thread. (and running 1/6 or 1/8 times slower compared to stage I)

Maybe 6.4 MHz would be good !?

[lilltroll]

Changing to 2.30 instead of 1.31 for the filter coefs, makes it possible to run the IIR filter in 8 or 10 MHz.
(8 MHz gives some more SNR du to better rounding)

With help of LSUB it is possible to clear 2 registers in one instruction, only using 9 instructions per BiQuad,

Code: Select all

lsub r10,r11,r0,r0,r0
maccs  r10, r11, b2, r7  // B2*X2  frees r7
maccs  r10, r11, b1, r6  //B1*X1
in r7, res[r0]     //reallocates r7
out res[r1],r8
maccs  r10, r11, b0, r7  // B0*X0
maccs  r10, r11, a2, r9  //A2*Y2 frees r9
maccs  r10, r11, a1, r8  //A1* Y1
shl r9,r10,2

Since r0 is a channel resource, the LSB must be 0.

[MaxFlashrom]

Remember that you will need to frequency shift the RF samples to baseband, not just sample-rate convert and low-pass filter. This is a non-linear operation changing the frequencies. This will shift the RF down to base band and transform the signal to IQ quadrature.
You can do this digitally by multiplying by a e^-jwt . This complex signal can be generated easily without the need for a lookup table.(start with 1+0j and repeatedly multiply my e^-j(wstep) to generate the next point)

Once the signal has been down-shifted then it can be sample rate converted and bandpass filtered with a decimating filter at much lower computational requirement. The usual polyphase implementation only calculates the required samples at the new lower rate. You may wish to consider the use of Cascaded-Integrator-Comb (CIC) filters. This may not buy much as a single cycle MAC is as good as a simple add.

See http://en.wikipedia.org/wiki/Digital_down_converter for helpful picture.
I saw this too, which may provide inspiration:
http://www.altera.com/support/examples/ ... c-fir.html

Regards
Max.

[ahenshaw]

Thanks for the post. I knew about that the I&Q conversion, but it looked like the low-pass filter was the computational killer. I had not seen your last link, but I will review.

[lilltroll]

I looked into CIC and polyphase filters as well, wondering what was most efficent vs. result on a XMOS that already includes the MAC.

I have written a C program that transform normalized double float DF-II coefs to the format needed for the 2.30 MACCS.
(Scaling more or less)

One way would to be using 2 threads @ 10 Mhz inout rate, the output of the second thread would output a downsampled signal with a factor 4 or 5 without touching the 0-200 kHz band.
Thus, we have 6 threads left that can run in 33 MHz each without effecting the 2 other threads, (if they run in a pipe). In total you would end up with a 16 order filter and 2 downsamplings on one core. The decimation can very easily be included in the ASM, just delete several out instructions. This will cost you one core per channel @ 10 MHz, and each thread would run some ASM filter code that is "almost" the same on every thread.

An other solution would to be running 2 channels at 5 MHz, if you need more than 2 cores left.

From my understanding the CIC filter would interfere with the band 0-190 kHz much more, compared to a multistage IIR solution.

[lilltroll]

What is the end purpose, are we talking stereo FM radio, or is it a "digital" transmission of data ?

[ahenshaw]

Amateur Radio software-defined radio. Ideally (which I don't think is possible), it would be great if an XMOS processor could perform the digital-down conversion of a 12-to-14 bit, 65 megasamples-per-second signal. Assuming that is not feasible, I'd like to know how fast it could be done.

[lilltroll]

Amateur Radio software-defined radio. Ideally (which I don't think is possible), it would be great if an XMOS processor could perform the digital-down conversion of a 12-to-14 bit, 65 megasamples-per-second signal. Assuming that is not feasible, I'd like to know how fast it could be done.

Using a 1.55 Core Voltage on a 90 nm Intel Prescott and water cooling made it possible to run it over 4 GHz.
If you can overclock it stable to 2.6 GHz, I can help you :mrgreen: