I'm sure there must be an actual formal description of the 20-pin connector signals but I've dug through tons of PDFs and can't find anything concrete except for the pinout in the XTAG-2 Hardware Manual, which says which pin is which but not whether/why they're needed etc. So for example it took me way too long to figure out that the only reason the XK-1A schematic is dorked up with buffers is because of the erratum about drive strength on some of the pins, and even there it only matters if you're going to daisy-chain multiple XK-1As. (Um, right?) The LED example doesn't bother so neither will I (but it sure goes through a lot of 2N7002s deciding when to reset!).
ANYWAY so my question is: if I want to build a small board with an XS1-G4-144BGA on it, which I'm hoping to be able to program/debug with XDE, can I get away with having only the JTAG pins (plus DEBUG -- right?) or are the XMOS Link pins required too? I ask because I'm planning to use the USB library on core 0, and it stomps on the Link pins (among many others). Or does that matter only during loading (when the USB stuff hasn't taken over yet), and once things are running all debugging happens through the JTAG interface only? What DOES the XTAG-2 use the XMOS Link bus for? I assume the UART pins are for my own amusement only so none of the tools will notice if I leave them off.
Also: I'm choosing the BGA package because I'm using a toaster oven to solder and I've only barely gotten 0.5mm QFPs to work (lots of solder wick to clean up shorts) and have no confidence about 0.4mm ones, especially because they violate batchpcb.com's 8/8/20 design rules (although it's close enough that they say they could pass it manually). But I've never done a BGA before. If anyone wants to talk some sense into me about that, or just generally laugh at me, please do!
Thanks!!
John Wilson
D Bit
XSYS connector -- dumb question
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JohnWilson
- Active Member
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- Joined: Fri Oct 28, 2011 10:53 pm
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Bianco
- XCore Expert
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- Joined: Thu Dec 10, 2009 6:56 pm
Hello John,
You can drop the UART, DEBUG and link signals.
The UART signals are self-explanatory.
The debug signal is or can be used to synchronize multiple cores/chips at once with JTAG (halting execution at the same time).
JTAG still works fine without this signal, but if you have room for it I would connect it.
The Link is used to provide a fast data link between the system and the debug adapter with low overhead.
This is for example used in the XMOS Xscope software scope. However, the XTAG2 uses an XS1-L chip and you are planning to use a XS1-G chip. The links of L and G are incompatible with eachother so the xscope feature cannot be used at all. Leave the links on the XTAG2 connector unconnected if you use a XS1-G.
Skipping these signals and a few ground pins, you should be able to fit the JTAG signals and at least one ground signal onto a 10-pin connector (needs a small adapter to interface with the XTAG2 though).
About home-baked BGAs: I would only start with it if you don't get disappointed when it does not work.
You can drop the UART, DEBUG and link signals.
The UART signals are self-explanatory.
The debug signal is or can be used to synchronize multiple cores/chips at once with JTAG (halting execution at the same time).
JTAG still works fine without this signal, but if you have room for it I would connect it.
The Link is used to provide a fast data link between the system and the debug adapter with low overhead.
This is for example used in the XMOS Xscope software scope. However, the XTAG2 uses an XS1-L chip and you are planning to use a XS1-G chip. The links of L and G are incompatible with eachother so the xscope feature cannot be used at all. Leave the links on the XTAG2 connector unconnected if you use a XS1-G.
Skipping these signals and a few ground pins, you should be able to fit the JTAG signals and at least one ground signal onto a 10-pin connector (needs a small adapter to interface with the XTAG2 though).
About home-baked BGAs: I would only start with it if you don't get disappointed when it does not work.
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JohnWilson
- Active Member
- Posts: 38
- Joined: Fri Oct 28, 2011 10:53 pm
Wow, what a great answer -- thank you! DEBUG doesn't conflict with anything so I'll definitely hook it up. I'd found some mention of its being there to synchronize halts between cores but since I don't know the protocol, I don't understand the problem or whether it's needed when the multiple cores are all in the same package. Whatever, it's a freeby since it's not shared with a GPIO.
Disappointment is my middle name so I'll press on with the BGA (a friend has had a 100% BGA success rate with a frying pan, and my toaster has been good to me so far) but batchpcb.com is cheap so maybe I'll lay out a QFP128 version too as Plan B. I know better than to mess with QFNs! (Even though the L2 sounds like a winner otherwise.)
If what you just said isn't already in a manual (that I couldn't find), it should be! Thank you thank you thank you!
John Wilson
D Bit
Disappointment is my middle name so I'll press on with the BGA (a friend has had a 100% BGA success rate with a frying pan, and my toaster has been good to me so far) but batchpcb.com is cheap so maybe I'll lay out a QFP128 version too as Plan B. I know better than to mess with QFNs! (Even though the L2 sounds like a winner otherwise.)
If what you just said isn't already in a manual (that I couldn't find), it should be! Thank you thank you thank you!
John Wilson
D Bit