XS1-L2

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
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leon_heller
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Post by leon_heller »

I phoned XMOS about them, I should get them next week.

Here is the schematic so far:

http://www.leonheller.com/XMOS/XS1-L2/XS1-L2.pdf

I haven't assigned the pins yet.

The PCB will probably be similar to the XC-1 etc.


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lilltroll
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Post by lilltroll »

leon_heller wrote:I phoned XMOS about them, I should get them next week.

Here is the schematic so far:

http://www.leonheller.com/XMOS/XS1-L2/XS1-L2.pdf

I haven't assigned the pins yet.

The PCB will probably be similar to the XC-1 etc.
I can't find any symbols for the L2 on xmos.com (yet)
Could you share the Symbol-Lib for the L2 with me/us ?
Probably not the most confused programmer anymore on the XCORE forum.
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leon_heller
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Post by leon_heller »

I created my own symbols based on the schematic in the L2 reference design files. I got the footprint details there, as well, by importing the Gerber files. I've added a couple of fiducials to the footprint, to make assembly easier.

My PCB part won't be much use to anyone else, unless they use Pulsonix. I'll be creating a spreadsheet for the pin assignments later on, for pasting into the part editor, and I can then export everything as a CSV file, which will save people a lot of time when creating their own part with another package. They can import it into a spreadsheet and paste it into their part editor.
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lilltroll
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Post by lilltroll »

Folknology wrote:Is that gerbered example (in the package zip) actually approved for a 2 layer design or 4 only (it seems to have two plane layers GND +V?)

Are there still issues with using an L2 on a 2 layer only board?

regards
Al
If we connect USB 2.0 to XCore-I via ULPI, some pins cannot be used - which we can take advantage of to solve the 1.0 and 3.3 V issue :idea: :!: :?:

I think/hope there are many escape-solutions for all available pins with a 2- layer design with USB.

I routed this by hand (Eagle):
The four 1.0 mm drill holes in the top are for assistance when placing the chip by hand.
Put four 1.0 mm drills or whatever in the holes and move the chip upwards until it stops - then heat it up.
L2-escape.jpg
L2-escape.jpg (127.25 KiB) Viewed 3042 times
L2-escape.jpg
L2-escape.jpg (127.25 KiB) Viewed 3042 times
Probably not the most confused programmer anymore on the XCORE forum.
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lilltroll
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Post by lilltroll »

And the XTAG and ULPI seems to fit very simple without the need of 100 vias :)
L2+ULPI-escape.jpg
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L2+ULPI-escape.jpg
(90.77 KiB) Not downloaded yet
Probably not the most confused programmer anymore on the XCORE forum.
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Folknology
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Post by Folknology »

Wow Mika

That's fantastic work, I love the idea of ULPI/USB core usage, fits perfectly with my planned L2 design for Amino+. I am presuming you build the footprints manually from the gerber examples?
Being able to hit 2 layers rather than 4 is killer for me!

I would like to see some feedback from Xmos regarding your approach, we also need to get it tested of course.
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lilltroll
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Post by lilltroll »

Folknology wrote:Wow Mika

That's fantastic work, I love the idea of ULPI/USB core usage, fits perfectly with my planned L2 design for Amino+. I am presuming you build the footprints manually from the gerber examples?
Being able to hit 2 layers rather than 4 is killer for me!

I would like to see some feedback from Xmos regarding your approach, we also need to get it tested of course.
My idea is that heat from the central PAD can escape through the groundplane at "south" since no pins are used in the south row B when Using ULPI. If all B-rows are used - no Heat can escape through a copper plane with a 2-layer design.
The 1.0 V is carried around the Top-layer (around the Pad), and 3.3 V is carried around in the Bottom-Layer in the "north"

I used the gerber + the schematic for Low Cost Reference Designs for L2 , to see whaqt would happend when you added the ULPI.
Probably not the most confused programmer anymore on the XCORE forum.
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Folknology
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Post by Folknology »

Mika I really like you solution and think it could work, I would love to look closer at the layers, would you mind providing a gerber version for further inspection? I totally understand if you don't want to provide that given all of your work of course, I am very curious about the possibilities.

regards
Al
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lilltroll
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Post by lilltroll »

I did it in Eagle 5.8 so I could make it avaiable for free even to students.
You can use Eagle for free with smaller 2-layer cards.
It's intended to be as open as possible.
Since Eagle are used by many beginners - there is often some import features from Eagle in more expensive ECAD program.

You can also find a good lib. here:
http://www.opencircuits.com/SFE_Footprint_Library_Eagle

I will post gerbers and the Eagle-files in a new XCORE-project this evening - probably with 0402 size instead of 0603 size.
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Folknology
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Post by Folknology »

As an Eagle user myself that answer is even better :-)
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