The XS1-L1 has two JTAG IEEE1149.1 TAP(Test Access Port) controllers within. The TAPs control access to n-bit shift registers, or scan chains. One such scan chain accesses cells interposed between a chip's pins and its internal core; this is the boundary scan chain. It is not mandatory to perform any operation on this scan chain. and indeed when using the JTAG interface to program a chip's internals this is often ignored. JTAG is ready to go usually after power-up. The JTAG interface comprises TCK(Test Clock), TMS(Test Mode Select), TRST(Test Reset), TDI(Test Data Input) and TDO(Test Data Output). TCK is a clock signal used to clock in data to a finite state machine within each TAP. On each rising TCK the FSM moves to a new(or the same state) ;how it moves depends on the state of the TMS input signal on the rising edge of each TCK pulse.snoopy wrote:TMS won't show anything until the JTAG chain is set up. It should remain low until the boundary scan is complete and the JTAG is ready to go.
As far as I know (its been a while since I had a look at JTAG traffic), the TMS will remain low until the JTAG state is ready to change. Once it is ready, TMS will be high and on the next TCK it will change state, TMS will then go low again and remain low until JTAG state machine is ready to move to the next state again.
Do you get any data on TDI and TDO? If these don't work, the JTAG boundary scan will fail.
EDIT: Also check TCK. Without a good clock nothing will happen on any of the JTAG lines
On each falling edge of TCK data is clocked out of the target chip's TDO.
Asserting the asynchronous TRST signal puts the FSM in a known state, Test-Logic-Reset. The TAP FSMs can also be reset by holding TMS high and issuing 5 TCK pulses. One is then ready to go. To move from the reset state, TMS must = 0, on the next TCK rising edge. This next state is called Run-Test/Idle. It's not that useful and one must move on again to Select-DR-Scan, this requires TMS=1 on next TCK. So, you see TMS is doing a lot of transitions just to get started: it should be doing stuff!
TCK must transition, TMS must transition, data should be coming out of the XTAG TDSRC, going into XS1-L1 TDI(Mine clocks about 12 zeroes in before starting to clock loads of 1s). If the L1 is alive data must come out of its TDO pin, feeding the XTAG TDSNK. If you see nothing on TDO you're not winning! Check that TMS and TCK are not shorted to anything. Check that TDI and TDO are not shorted to anything.
You indicate the XS1 seems to be alive by the fact that it appears to attempt an SPI boot when you set the mode pins[3:2] to 11. I notice you have wired PCU_WAKE to ground rather than leaving it unconnected as recommended in the datasheet, though if the SPI boot seems to be doing its stuff this is probably OK.(I know, leaving CMOS inputs floating which may or may not have an internal pull-up/down makes me nervous too). The data is somewhat vague on whether this pin is active high/rising edge triggered and whether it should be high/low/don't care in normal woken operation. If one follows the datasheet and one's not using it to wake the chip from sleep this need not concern you.
You could try
from the command-line. So as not to conflict with the IDE, it is best to do this while not running that at the same time. This will query the board slowly.xrun -l --jtag-speed 100
If all is well you will see something like this:
Available XMOS Devices
ID Name Adapter ID Devices
-- ---- ---------- -------
0 XMOS XTAG-2 a3zvg42z L1
If stuff is not working it will say "None" or "Error" under Devices rather than the desired "L1"
Hope that helps