Two XS-L1 in a chain

[homerJ]

Hi,

I want to connect two XS-L1 devices via a XLink.
The master core boots from the SPI flash and then boots via the XLink the slave core.
This is the configuration of the mode pins:
master core: mode[3] = 1; mode[2] = 1;
slave core : mode[3] = 1; mode[2] = 0;

But what happens if i want to boot via the JTag?
The master mode pins should be configurated with mode[3] = 0 and mode[2] = 0.
But what about the slave core mode pins?
->change to JTag mode too or leave in XLink boot mode?

Greetings#

[segher]

You probably want to boot both devices in "JTAG mode". The L2 (which is just
two L1s connected together, but via an internal link) does this as well.

[Woody]

Segher is right. Select boot from JTAG on both.

Booting from JTAG stops the boot code from attempting to boot via either link or SPI. This means that the ports are not activated (SPI) or link B (and the internal links on an L2) are not enabled and a channel end is not taken (link).

If you didn't select boot from JTAG, then when you start debugging you may get inconsistent results because the starting condition will differ. FYI though, when I inadvertantly don't change the mode pins to boot from JTAG, nothing bad usually happens and I don't usually notice my mistake as everything seems to work.

So you may see some issues if you don't select boot from JTAG when that's what you are doing, but don't be surprised if you don't see issues!

[segher]

If e.g. a core is set to boot from SPI, and you have a valid program in that SPI, it will
start to run and do all kinds of stuff to your resources before you can stop it via JTAG.
Not good if you want to upload a different program.

If there is no valid program in SPI, that's not a problem of course.

When you have a multi-core system, in some cases you might want to boot only
one core as JTAG, for example boot the other one via link (from that first core);
or perhaps the program on that second core is not something you want to debug
right now. You can of course boot it from JTAG and make it run whatever you
want to run ;-)

If you're using jumpers to set boot mode, I'd do them separately per core; if you're
using TRST to force JTAG boot mode, just do it on all cores.

[rp181]

if you're
using TRST to force JTAG boot mode, just do it on all cores.

Clarifying question: During normal operation, TRST_N goes low for a period of time and high again to reset. When programming, does the XTAG hold TRST_N low? I do not understand how the TRST_N signal is able to automatically select boot mode as the TRST_N signal given by the XTAG header is the same as the XTAG's L1 TRST_N signal.

EDIT: So when the XTAG pulls it's own L1 chip low, it does not matter as the JTAG is not being used?

[segher]

I do not understand how the TRST_N signal is able to automatically select boot mode

You add circuitry for that. See for example the XC-1A or the XK-1 revB schematics
(not the XK-1 revC, which has a jumper instead).

I don't understand the rest of your questions, could you rephrase?

[hazamix]

i have same design with homerJ
my problem is when i use debug mode both chip work very well
bug when i set master chip to SPI mode and try to use flash boot and work
almost time were fail , only few times boot complete and work fine
and i use oscilloscope test all reset and power look good
but i find my 2 wire xb-link a pin cannot down to 0v
it will be hold on 2v and i try hardware fix let all pull low
but problem still happen

how could i fix this problem?


p.s our design is use master chip boot and link to slave chip
master chip mode set JTAG or SPI ; slave chip set always XBlink

[Bianco]

What is the external clock/oscillator frequency and what are the XMOS PLL mode pins settings?

[hazamix]

osc is 20MHz and mode 0/1 were set 11