XS1-G3?

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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segher
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Re: XS1-G3?

Postby segher » Wed Nov 03, 2010 2:23 pm

I think so yes.

But don't despair, I was being silly, you can have 65536 nodes, by simply numbering
them consecutively in binary. You cannot wrap in general, but you can still put a 0000
in the middle by flipping the top bit in the node ids. The direction for bit N is right if
bit N in the node id is 0, and left if it is 1 (before flipping the top bit).

Is 32768 L2s enough for you? :-)
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Paolomio
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Postby Paolomio » Wed Nov 03, 2010 11:10 pm

Thanks, segher!

I see how your scheme works, and that seems correct on inspection for 16 L2's. Unfortunately, I will need a few more chips than this--in my system I could have as many as 128 L2's in a chain for some configurations, and the routing needs to work for any number or this architecture isn't scalable, right?

Say the nodes are numbered sequentially from FFFF on the left to 7FFF on the right, and we have 32768 L2's. (XMOS stock jumps in price!)

FFFF, FFFE, FFFD, FFFC, ..., A000, 9000, 8000, 0000, 0001, 0002, 0003, ..., 7FFE, 7FFF

So the routing table for node 0000 (the master) would be LRRR RRRR RRRR RRRR, as you suggest. Now remember, I'm using links connected to the switch on core0 (e.g., node 0000, 0002, etc.), so node 0001 is accessed between the internal switches. (As an aside, it would seem some direction configuration is needed to access this switch too, since this really looks like a pipeline of pipelines.) But for the sake of argument, let's just look at a single chain to see if we can make that work. If that works we can go back later and modify for a pipeline of pipelines.

So, assuming 0001 is on the right of 0000, and 0002 is on the right of 0001, the routing table for 0001 is LRRR RRRR RRRR RRRL. The routing table for 0002 is LRRR RRRR RRRR RRLR, for 0003 it is LRRR RRRR RRLL and so on. In short, the routing table in each node is (NOT nodeID) ^ 0x8000, assuming left is dir 0, and right is dir 1.

On the left side, the routing table for each node is just the nodeID.

I think this works...check it...but now what to do with the other core and switch in the L2? I think there is an UP direction in this table somewhere... <sigh>

Paul
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segher
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Postby segher » Thu Nov 04, 2010 4:30 am

That numbering can work, but why not do it simpler, like (node ids in binary):
100 101 110 111 000 001 010 011
RRR RRL RLR RLL LRR LRL LLR LLL

I don't remember how the L2 cores are connected, remind me? The datasheet
won't open for me (it's not a valid pdf, for older readers).
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Paolomio
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Postby Paolomio » Fri Nov 05, 2010 4:50 am

I think this scheme will work, but I'm not exactly sure why it's "simpler."
segher wrote:I don't remember how the L2 cores are connected, remind me? The datasheet
won't open for me (it's not a valid pdf, for older readers).
It's basically just two L1s in a package with the two switches connected by four links, with two links on each switch unconnected and two links on each pinned out on the package.

To answer my own question from above, for each core0 switch, the the bit 0 direction needs to be "UP", whatever direction is already being used by the internal interconnect links. I dont think anything must be changed on the core1 switches, other than to set the nodeIDs.

I'm out of town so I can't experiment to see what these links are set to directionwise, but will do that when I'm back in a couple of days.

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