XS1-G3?

[Folknology]

I always find product/part numbering interesting as it can often reveal hidden detail.

In addition to the thread about missing ports http://www.xcore.com/forum/viewtopic.php?f=7&t=113 I got to thinking about the Chip numbering:

We currently have L1,G2 & G4. If we ignore the letters this clearly shows a binary progression (2**x++) corresponding to the number of cores. Thus the next in the series is likely to be G8, which would be completely awesome, 64 threads, 3200 Mips just wow...

But lets just pause a minute and consider other possibilities why are their Ls and Gs. Does the L stand for lower power? I have obviously missed some of the history here..

But where do the Ls go moving forward, obvious a l0.5 doesn't make sense, which suggests L2 and maybe even L4,L8 etc...

But wait what about the other possibilities, AMD shook things up with Tri-cores, this concept applied at XMOS could lead to an L/G3 or L/G6.

So what do you think could be coming and what would you like to see, alternatively is there another alternative hidden in the numbers?

Thoughts?
;-)

[leon_heller]

I saw somewhere that XMOS thinks that a maximum of four cores is all that most users will want, although they might develop an eight core chip in the future if there is sufficient demand.

Leon

[jonathan]

I saw somewhere that XMOS thinks that a maximum of four cores is all that most users will want, although they might develop an eight core chip in the future if there is sufficient demand.

Leon

Where did you see that?

I was told the AMD three core chips were four cores with a dead core, due to poor chip yield.

[Folknology]

Well the Llink specs go from A through to H which suggests an 8 core max before the ports break.

[leon_heller]

I saw somewhere that XMOS thinks that a maximum of four cores is all that most users will want, although they might develop an eight core chip in the future if there is sufficient demand.

Leon

Where did you see that?

I can't remember. It might have been mentioned at the XMOS seminar I went to just after the chips were launched.

Leon

[dave]

The XMOS interconnect architecture can route messages between up to 65536 XCores with up to 256 channels on each XCore.

The first 16 bits (the first two tokens) of each message are used to route to an XCore. The first few bits route to a switch and the remaining bits (of the 16) route to an XCore connected to the switch. The next 8 bits (next token) route to a channel within the XCore.

An L1 has a single XCore connected to a single switch; a G4 has four XCores connected to a single switch. Note that the XMOS Links are connected to the switches, not the XCores.

Any number of switches can be connected - you can see an example of this in the Youtube videos about XMOS Links and the XK-1 where a number of XK-1s are connected via Links. A variety of network structures can be used depending on performance requirements; these include n-dimensional grids, hypercubes and trees - or networks which combine different structures.

Each switch contains a table which is programmed according to the interconnect structure. The switch uses the table entries to find the direction to forward arriving messages. The entries are set up so that each message is forwarded in a direction that moves it closer to its destination.

The number of XCores in specific products will be determined by need and economics. Several XCores can be combined on a single chip using a single switch or - for larger numbers - a network of switches. Chips can be combined on substrates and/or boards using the XMOS Links.

There is an explanation of the interconnect and an example in the presentation at http://www.cs.bris.ac.uk/~dave/cpa.pdf. The detail is in the System Specification documents on the XMOS site.

[Heater]

Are we likely to see a chip that is just a switch that can be used to interconnect many other normal devices with a few cores each?

[Paolomio]

Each switch contains a table which is programmed according to the interconnect structure. The switch uses the table entries to find the direction to forward arriving messages. The entries are set up so that each message is forwarded in a direction that moves it closer to its destination.

This seems straightforward, but there seems to be something missing in the implementation, or more likely in my understanding. Here's my scenario:

I have a large number of L2's connected "left" and "right" via xlinks, in a linear array. One of them, in the middle, is the master. Any core needs to be able to talk to any other core, and especially to the master, and vice versa.

Here's the catch: the xlinks actually used to interconnect both left and right are on the same switch, connected to the same core (core0 in this case). Since there is only one set of registers per switch (and in the case of an L2, each switch is connected to one of two cores), there doesn't seem to be a good way to specify the direction bits such that there isn't a block along the way--at least not that I can find.

If the left and right links were on different switches then I could easily set the direction bits in the left to dir 0, and the direction bits on the right switch to dir 1, and it would (conceptually) work.

But since the links are on the same switch, there is only one set of direction routing bits, and this scheme can't be implemented.

In the absence of a way to set the direction on a per-link basis (not just on a per-switch basis) I don't see how you can make an architecture such as I describe work.

Dave, can you point out where I've gone astray?

Paul

[segher]

In a chain, you can set the node ids to

0000, 0001, 0003, 0007, 000f, ... , 7fff, ffff, fffe, fffc, ..., c000, 8000

(so max. length 32).

Perhaps it's nice to make the master mode #0, and it's in the middle;
let's do that instead.

ffff, fffe, fffc, ..., c000, 8000, 0000, 0001, 0003, 0007, 000f, ... , 7fff

Now for e.g. node 000f, anything with bit 15 a 1, so different from its own,
should go to the left. Anything with bit 15 the same (a 0) but bit 14 different,
should go to the right. 15..14 the same 13 diff, to the right; ... 15..5 the same,
4 different to the right; 15..4 the same, to the left.

For the master node, you have node id 0000, and you get for the direction
table (15..0) LRRRRRRRRRRRRRRR.
For the Nth node on the left (counted from the master), you have node id (top N
bits set), and you get for the direction table (15..0) RRRR...LLLL, with N Ls.
For the Nth node on the right, you have node id (bottom N bits set), and you get
for the direction table (15..0) LRRR...LLLL, with N+1 Ls total.

Does that help? I hope I didn't make any silly mistakes, better verify it :-)


Segher

[lilltroll]

Does 32 Nodes mean 16 or 32 L2 ?

I guess 16, since a L2 =2*L1, meaning that it has 2 switches on chip !???