Sharing CLK_13M and TCK across three L1s

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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russf
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Sharing CLK_13M and TCK across three L1s

Postby russf » Sun Mar 06, 2011 9:59 pm

I have a small board design with three L1s. One is 64, the other two are 128 pin.

I'm distributing the output of the NC7SZU04 inverter (CLK_13M) and the XSYS2 TCK around the three devices using two STCD1040s (Yes, i could use STCD1030 that only has three channels, but nobody stocks them).
http://www.st.com/stonline/books/pdf/docs/13823.pdf

The STCD1040s is a $3 part, and I'm wondering if there is a cheaper way. Feels a bit like overkill, but you can spoil a ship for a ha'porth of tar. Any ideas?

Edit: Hmmm... There is 74LVC841A, used in the XMP64 design, It's a big 24 pin beast, but it will handle both sets of clocks.

Another Edit: And I can save a bit more space by going to : 74LVX373MTC. But looking in more detail, it has an UGLY pinout. I'll have to throw a bunch of vias on the D inputs, to keep the Os clean. Hmm..

--r.
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segher
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Postby segher » Mon Mar 07, 2011 12:51 am

Maybe I'm crazy, but can't you just tie the input lines together? Should work for the
TCK at least, as far as I know.
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russf
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Postby russf » Mon Mar 07, 2011 1:29 am

Thanks segher,

I was concerned about interactions at the clock inverter output. I'd be happy to hear that I can drive three L1's on a 160mm board from a single oscillator circuit.

I'll plan the circuit with the buffering, and try shorting without the device, unless I hear otherwise by Monday morning PST.
Corin
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Postby Corin » Mon Mar 07, 2011 11:46 am

Hi Russ,

We would recommend buffering them - just use standard logic triple output buffers (e.g. a NC7NZ34).

This is due to the issues detailed in the Errata of the datasheet (section 11).
To guarantee a logic low is seen on the following pins, the driving circuit should present an impedance of less than 100 ohms to ground...

Usually this is not a problem for CMOS drivers driving single inputs, however, if one or more of these inputs are placed in parallel, additional logic buffers may be required to guarantee correct operation.
For static inputs tied high or low, the relevant input pin should be tied directly to GND or VDDIO.
Cheers,
Corin
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russf
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Postby russf » Mon Mar 07, 2011 12:09 pm

Thanks Corin,

I appreciate the prompt response! I'll do as you suggest.

--r.

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