Why do I get Cannot load image, XCore 0 is not enabled?

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migueljds
Experienced Member
Posts: 78
Joined: Thu Dec 10, 2009 7:08 pm

Why do I get Cannot load image, XCore 0 is not enabled?

Postby migueljds » Mon Jul 15, 2019 5:06 pm

When bringing up a new board design or during production test the following
error my be returned from xrun: Cannot load image, XCore 0 is not enabled.
This error message means that the XTAG or XTAG2 JTAG debug adapter can
access the JTAG tap on the device, but cannot access the XCore tap on the
device.

There are many reasons why this may be the case including:

1. The JTAG interface to the XCore has been disabled in the OTP security
register.

2. The device is being permanently held in reset by the RST_N signal.

3. No clock is being supplied to the device; or the clock frequency
supplied to the device is unsuitable for the selected PLL multiplier. The
PLL multiplier is set using the MODE pins and should be configured so that
the XCore boots up at or below its maximum frequency. Further details on
the MODE pins can be found in the relevant device datasheet.

4. The VDD Core supply is outside of tolerance (see the device datasheet).

5. The VDD PLL supply is outside of tolerance (see the device datasheet) or
not present, or has a filter with too high a resistor. This will mean that
the PLL is not locked and hence the XCore will be kept in reset.

6. The power supplies have not been correctly sequenced. The VDDIO (and
OTP_VDDIO if present) supply must be within specification (3.0V-3.6V)
before the VDD Core supply is turned on; see the datasheet for details.

7. The device, especially the ground paddle, has not been correctly
soldered to the board. This can either be in the form of not connected
solder joints or shorted solder joints to other pins, ground or power.
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Thomas
Experienced Member
Posts: 66
Joined: Fri Feb 05, 2010 12:34 pm

Postby Thomas » Wed Nov 13, 2019 10:13 am

Regarding Reason number 3:
Make sure that the Oscillator value in the .xn file matches the frequency of the input CLK
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ccrome
Active Member
Posts: 61
Joined: Wed Sep 23, 2015 1:15 am

Postby ccrome » Sat Aug 29, 2020 10:23 pm

migueljds wrote:
Mon Jul 15, 2019 5:06 pm

3. No clock is being supplied to the device; or the clock frequency
supplied to the device is unsuitable for the selected PLL multiplier. The
PLL multiplier is set using the MODE pins and should be configured so that
the XCore boots up at or below its maximum frequency. Further details on
the MODE pins can be found in the relevant device datasheet.
Yep, this one for me. Thanks for the answer. Somehow 1/10 oscillators got programmed incorrectly to 45 MHz instead of 24MHz.

Thanks,
=-Caleb
fabra
Member
Posts: 14
Joined: Sat May 09, 2020 4:20 pm

Postby fabra » Wed Nov 04, 2020 9:26 pm

How did you figure out the frequency that the device was programmed for?

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