How to use MCLK other than 24.576MHZ for 48K Audio

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amninder
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How to use MCLK other than 24.576MHZ for 48K Audio

Postby amninder » Thu Jan 28, 2016 2:30 am

I am using the XMOS Muti Channel Audio Kit for audio evaluation and it uses the MCLK rate = 24.576Mhz for streaming audio over I2S lines.

How can I use a different MCLK , like (12.288Mhz) for audio streaming purposes. Is there any firmware changes required?

I simply tried feeding an external MCLK of 12.288MHz to the XMOS controller in eval kit . I do listen to some audio output but the pace/speed is very slow and hard to make sense.

So, if anyone have tried a different MCLK , can you please share the procedure to enable it.

Thanks

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infiniteimprobability
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Postby infiniteimprobability » Thu Jan 28, 2016 5:13 pm

Look in customdefines.h

You'll need to adjust the following:

/* Master clock defines (in Hz) */

#define MCLK_441           (512*44100)   /* 44.1, 88.2 etc */
#define MCLK_48            (512*48000)   /* 48, 96 etc */
 
to
 
/* Master clock defines (in Hz) */
#define MCLK_441           (256*44100)   /* 44.1, 88.2 etc */
#define MCLK_48            (256*48000)   /* 48, 96 etc */
amninder
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Postby amninder » Tue Mar 01, 2016 6:32 am

Thanks for the reply , infiniteimprobability.
The solution you mentioned would require a firmware update to support different MCLK.
Is it possible to do it at runtime i.e without updating the firmware?
I
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Ross
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Postby Ross » Tue Mar 01, 2016 6:32 am

amninder wrote:Thanks for the reply , infiniteimprobability.
The solution you mentioned would require a firmware update to support different MCLK.
Is it possible to do it at runtime i.e without updating the firmware?
I
The codebase doesn't currently support this, though I don't believe it would be too hard to add.

Alternatively, you could use a clock generation IC with multiple outputs, one fixed at 24.576, say, and another that outputs a configurable multiple of this to a DAC. We've used this scheme before (an SI part) and actually used a 3rd output to drive the 24MHz xcore system clock.
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Ross
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Postby Ross » Tue Mar 01, 2016 11:18 am

What board are you using? If it has a fixed MCLK setting the software different to the hardware is going to cause issues.. Some boards have a configurable MCLK source (e.g. some sort of clock generation IC) in this case you can change it.
amninder
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Postby amninder » Fri Mar 04, 2016 5:38 am

I am using the same XMOS chip used in Multi-Channel-Kit in my custom design Hardware. In my hardware, I have 2 different MCLK sources like 12.288MHz and 24.576MHz which I can change on the fly but cannot fully use this feature as I have to update the firmware to switch between different MCLKs. So, my question is if it is possible for one firmware image to support different MCLKs?
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Ross
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Postby Ross » Fri Mar 04, 2016 12:04 pm

Not without modification. The base code supports one fixed MCLK for 48k etc and another for 44.1k etc.
amninder
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Postby amninder » Mon Mar 21, 2016 10:01 pm

Hi ,

In our project, we are trying out running an MCLK with a different frequency than what the reference design had. It has 24.576 and 22.5792 MHz. We'd like to try 9.6 MHz. To start with, I’m trying to build (set at compile time) an image that would support only an MCLK of 9.6. I changed a few obvious things, but seem to be missing something, as the compiled image behaves badly.

I’ve defined a MCLK_MULTIPLE to hold the ratio between MCLK and base sampling rate. (Default 512.) I’ve set this to 200 and set MCLK_441 and MCLK_48 accoringly. I also set DEFAULT_FREQ to 48000 as I don’t expect to use the 44.1 family in this case. There were a couple of places in devicedefines.h and audiorequests.xc with hardcoded values of 512 which I changed to this define flag.

It appears that something isn’t kosher, because it looks like there are at least some threads hanging. Endpoint0 isn’t responding and worse.

Any suggestions on the steps to use 9.6MHz MCLK?
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infiniteimprobability
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Postby infiniteimprobability » Tue Mar 22, 2016 11:50 am

Any suggestions on the steps to use 9.6MHz MCLK?
You're going to struggle without a PLL..

9600000 / 48000 = 200. It's an integer which is good, but you need to generate 64 BCLKs per sample pair for I2S.

9600000 / (48000 * 64) = 3.125... Hard to get a divider to give you that without going up first, hence PLL suggestion.

You *might* be able to something really whacky such as:

Start the I2S frame off on 9600000 / 200 (gets you your LR clock first edge) and then use core clock (500MHz) / 162 to get 3086419.753Hz for your BCLK. It will be 0.3 BCLK cycles too early by the end of the I2S frame but you might get away with it as it's less than half..

It's a bit messy and will require a re-write of the inner loop, but maybe doable if the benefits outweigh the effort
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Postby twittich » Mon Jan 13, 2020 1:56 pm

Hello
i'm trying to get it work with 24 MHz and if i set the definition "MCLK_48" to (500*48000) there is no more output over i2s.
And the i2s lrclk is 46.8 kHz which is exactly 24000000 / 512 but it has to be 48 kHz ....

Thanks in advance.

Update: Fixed it by hardware changes....
Last edited by twittich on Mon Jan 20, 2020 11:57 am, edited 1 time in total.

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