TDM8 timing of USB Audio reference software

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
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TDM8 timing of USB Audio reference software

Post by rkn »


I am working with USB Audio 2.0 Device Software on XE216-512-TQ128 (custom hardware). I've sucessfully configured it for TDM8 master operation but I am wondering about the timing specification of the TDM stream. Could not found anything in the docs but I need to configure my DACs right. Thus, can anybody specify things like rising or falling LRCK edge, rising/falling edge BCLK and data delayd by one cycle or not?


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Post by infiniteimprobability »

the TDM8 master implementation uses the single sclk cycle duration high pulse per frame. The frame clock is high for the first data bit of the TDM frame.
Page 24 of the CS4384 datasheet shows this nicely.
The relevant piece of code is:

#ifdef I2S_MODE_TDM
if(frameCount == (I2S_CHANS_PER_FRAME-2))
p_lrclk <: 0x80000000;
p_lrclk <: 0x00000000;

ie. it will send a 31 x low and the a high at the end of each frame.

When in slave mode it syncs off the rising edge of the frame clock.

I have seen both single sclk width pulses or 50:50 (square) frame clock implementations of TDM8 master. I am not aware that there is a standard as such although the rising edge is generally the important one.
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Post by akp »

data is usually output on falling edge of bclk and sampled on rising edge i am pretty sure