xCORE pins, ports and xlinks precedence Topic is solved

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keno
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xCORE pins, ports and xlinks precedence

Post by keno »

Hi Everyone,

After having read this post, I would just like to confirm:
http://www.xcore.com/viewtopic.php?p=24627#p24627
On an xCORE-200 tile[1] with USB:
The USB consumes P8A, P8B, P16A, P32A, but I can still use P4A and P4B and associate pins X1D2 through X1D9 for IO?
Along the same lines, my XUF216-512-FB236 is using xlink1 for xConnect/xScope. However I can still use all of P32 - Pins X1D49 through X1D70 for Input/Output?

Thanks,


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mon2
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Post by mon2 »

Hi.

Reference:

https://www.xmos.com/published/xcore-20 ... ion=latest

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https://www.xmos.com/published/xcore-200-devices-portmap?version=latest
The USB consumes P8A, P8B, P16A, P32A, but I can still use P4A and P4B and associate pins X1D2 through X1D9 for IO?
Yes.
Along the same lines, my XUF216-512-FB236 is using xlink1 for xConnect/xScope. However I can still use all of P32 - Pins X1D49 through X1D70 for Input/Output?
No. Since both, xConnect / xScope and the I/O pins are physically bonded onto the same pins, only one function can be used. For the USB implementation, there are internal muxes steering the logic around so that you can have your external P4A & P4B access using the same port pins while internally, the USB function can be enabled. Perhaps you can consider to use other (free) xlink pins for your project?
keno
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Post by keno »

Thanks Mon2!
keno
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Post by keno »

Can I use the parts of P32 that aren't occupied by xlink1 for general IO? P32A10 -> P32A19? Send or Rcv?
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mon2
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Post by mon2 »

Can I use the parts of P32 that aren't occupied by xlink1 for general IO? P32A10 -> P32A19? Send or Rcv?
P32A10..P32A19 are overlapped with the xlink2 group so if xlink2 is not enabled for your project then yes, these GPIO pins are available for your access.

A general comment on XMOS ports, at leas for the older XS1 series, all of the port pins of the group must operate in the same direction. That is, if in output mode then each port pin of that group must also be an output and respectively the same for input mode. The xcore-200 series does not have this restriction but have not personally tested this mode of operation.

For this example, if you have xlink1 enabled and you perform a write (output) onto P32A then P32A0..P32A9 will be "waxed away" (due to the physical pins being mapped to the xlink function) but P32A10..P32A19 will be sent to the outside world. Just keep in mind that these group of pins are on Tile[1] so be sure to write your code to access them accordingly. The prefix of the port pins gives away which tile you are working with so for these pins X1 prefix (tile[1]) vs. X0 (tile[0]), etc. Otherwise you will be shooting blanks. That was a common question on how to light of the LEDs on the XMOS XCORE-200 audio board where there is a matrix of LEDs.

reference reading:

http://www.xcore.com/viewtopic.php?f=26 ... age#p33891

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http://www.xcore.com/viewtopic.php?f=26&t=6676&p=33891&hilit=XU208+questions+about+port+usage#p33891
Example of how to access port pins on different tiles:

http://www.xcore.com/viewtopic.php?t=4401

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http://www.xcore.com/viewtopic.php?t=4401
keno
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Post by keno »

Again, my thanks Mon2!
The example of accessing ports across tiles will be especially useful!
Until we get safe usage guidelines for mixed IO mode for a port, I will try follow the official rules.
XUF216-512-FB236 Datasheet Section 4 pg 6 top paragraph says:
"All pins of a port provide either output or input, but signals in different directions cannot be mapped onto the same port."
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