Newbie question: where are the high-i/o boards ?

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SpacedCowboy
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Newbie question: where are the high-i/o boards ?

Postby SpacedCowboy » Fri Aug 24, 2012 9:59 pm

So, having looked at the XMOS, it seems pretty cool, and well worth getting to know. I was looking at the G4, and that would seem to have 4 cores, each with 64 i/o on them, for a total of 256 i/o. That's a lot of i/o :)

What's not obvious is if you can actually get a (cheap :) dev-board that exposes all these wonderful i/o ports. The best option I can find seems to be the XC-2, but that only has 84 i/o pins - I realise that some are lost to the ethernet, XTAG, whatever, but seriously, where's the rest of the pins gone ?

What I'd like to do is put a video-decoder, 2x1MB SRAM chips, and an ethernet device (amongst other things like ADC, flash, etc.) on the board. I don't expect to find a board like this, but ideally I'd be able to find a board that exposed sufficient pins that I could plug in the missing bits.

Ideally, of course, we'd get a card (Best would be DDR2 SDRAM DIMM which'd give 240 pins, but I'd settle for a x16 PCIe card which'd give ~160 pins) that we could plug into a "motherboard" with a standard mating socket. If you really want to go for it, something like http://www.enterpoint.co.uk/moelbryn/darnaw1.html gives you an ideal solution - an easy re-usable prototyping board with some useful on-board things (memory, clock, SPI flash,...) that you can plug into your personal "motherboard" and let rip... The Darnaw1 isn't even too expensive, at £95.

[Edit]
To give you an idea of what I mean regarding the PCIe card slot idea, attached is one I did for the Atmel AVR chip - all the port lines are available on every slot, as well as CLK (@20MHz, this works surprisingly well :), GND, 5v, 3.3v and Vin (normally 9-12v). This is using PCIe 1x, but with the larger number of ports on an XMOS, we'd need the larger-sized slot. It's simple, but very flexible. I have a number of boards (SRAM, ethernet, switches, LEDs, LCD, Serial port, ...) that slot into the PCIe slots and do whatever I want - all I have to do is make sure I design the slot-boards to not conflict. I had plenty of i/o per socket so I used some of the spare lines to identify which slot the board was in. I figured it might come in useful someday [grin].

In the photo, the board on the left is power, the middle is serial/SPI flash, and the right is the CPU. The "motherboard" is a completely passive backplane.

Oh yeah, the serial/flash board has header switches (yellow) to enable/disable the serial port connection and the flash SPI connection. If the header switches aren't in the closed position, those components are isolated from the backplane. It's infuriating to me when I need "just one more i/o" as I stare at the LED that the board designer "thoughtfully" hardwired to a port line. Make it possible to isolate the LED and provide me the port as an i/o already! Grrr.
[/Edit]

So, am I missing something? Am I dreaming? Or is it a case of "here's the tools, mate, off you go" ? :)

Please don't take this the wrong way, the xmos looks like its going to be really fun to work with, but too many times in the past, I've bought a dev-board thinking "this is going to be fine", and later realised I'm short of <insert X here>. The for-sale boards seem to be pin-restricted, so if there's other (affordable, I don't want to pay $1k for the XDK XS1-G!) options, I'm all-ears :)

Cheers
Simon
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rp181
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Postby rp181 » Sat Aug 25, 2012 3:38 am

Some key points you seem to be missing:
1) DDR RAM is double data rate memory, which means it performs operations on both the rising and falling edges. As far as I know, XMOS only can do one. This doesn't make it unusable, but slower and less memory access.

2) While it does have many IO pins, not all of them are usable for anything. There are ports that are disabled when using ULPI USB, there are ports that you need to use for XLINKs, there are ports of different widths (for example, there are 32 bit ports that can only be used as such, not 1 bit ports). A lot of the things you listed require many 1 bit IOs.

3) Connecting the hardware is one thing, but driving the hardware is a completely different animal.

However, XMOS does indeed have a lot of IO to work with. Not all of them are broken out on dev kits to presumably keep costs down. Breaking out all the IO on a G4 would make the board both bigger, need more layers, and ultimately more expensive.

I myself have made a board with 4 L1s (easier soldering), and there was plenty of IO for USB, full 4-wire XLINK connections, 8 SPI ADCs, and 4 SPI DACs (none of them share buses), with some IO leftover.
SpacedCowboy
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Postby SpacedCowboy » Sat Aug 25, 2012 4:21 am

rp181 wrote:Some key points you seem to be missing:
1) DDR RAM is double data rate memory, which means it performs operations on both the rising and falling edges. As far as I know, XMOS only can do one. This doesn't make it unusable, but slower and less memory access.
I wasn't suggesting using the signals on the interface as they are, I was suggesting an electrically incompatible approach, leveraging the availability of commodity parts (the DIMM/PCIe form factor) in order to create a cheap passive backplane. If you wanted memory, it'd be up to you to create a signalling interface that worked for you (unless Xmos define well-known port usages or something) and that's it.

To be clear, the 8-bit AVR chip in the photo doesn't do PCIe :)
rp181 wrote:2) While it does have many IO pins, not all of them are usable for anything. There are ports that are disabled when using ULPI USB, there are ports that you need to use for XLINKs, there are ports of different widths (for example, there are 32 bit ports that can only be used as such, not 1 bit ports). A lot of the things you listed require many 1 bit IOs.
Whereas that may be so (and I did pick up on it from the datasheets), it seems to me that there's more than 84 available... Which is all that the 4-core ethernet board provides, and even then only parts of ports are available on that board (there's only 24 of the 32-bit bus available, as far as I can see, for example).
rp181 wrote:3) Connecting the hardware is one thing, but driving the hardware is a completely different animal.
[grin] I can't find anything too useful in the datasheet - all 20 or so pages of it... but I'm assuming they have enough oomph to drive an electrical signal the few cm or so to a (typically) high-impedance digital input. If not, then they're not terribly useful :)
rp181 wrote:However, XMOS does indeed have a lot of IO to work with. Not all of them are broken out on dev kits to presumably keep costs down. Breaking out all the IO on a G4 would make the board both bigger, need more layers, and ultimately more expensive.

I myself have made a board with 4 L1s (easier soldering), and there was plenty of IO for USB, full 4-wire XLINK connections, 8 SPI ADCs, and 4 SPI DACs (none of them share buses), with some IO leftover.
Looking at the 512-ball pinout, it seems to me you could (just about) get away with a 4-layer board. You'd have to have a split ground/power plane, which wouldn't be ideal, but would probably work "ok" at the relatively low clock speeds we're talking about. Hell, I've run 50MHz over 40-way IDC cable before now... It's not something you'd look at as the pinnacle of PCB design, but it'd probably work :) 4-layer isn't too expensive any more ($10/sq in for 3 boards at oshpark.com) for small quantities, and gets rapidly cheaper at medium quantity.

Maybe I'll give it a go. The real downside is having to gamble on how well the BGA is soldered to the board - and at 0.8mm separation, there's not too much wiggle room with my reflow oven. I had hoped someone would have done it before me, because I prefer *not* to dive into a new environment by designing the freaking PCB [grin] It's kind of useful to have *something* you know works when you're learning...

Simon.
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Allein
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Postby Allein » Sat Aug 25, 2012 9:36 am

Hi,
As a very experienced complex PCB designer, I would like to bring in some quick remarks on this thread topics:

1) G4 processor: as you maybe not know, the G4 isn't compatible with the new XC processors (L1 / L2 / ...) because of its 1st generation XLink. So, should you want to connect to another XC, then you'd be limited to G4 only ... It's a weak point, sufficient to have me leaving the G4 aside. So, I'm also going towards multiple L1 or L2 for achieving the desired number of XCores and I/Os.

2) 512 balls BGA: I've designed numerous PCBs with tens of large BGAs on-board, and I can tell you that you'll never be able to fan-out the inner signals to the outside using only four layers. Not speaking of connecting the power balls...
Don't forget that, with 0.8mm pitch, you are forced to use MicroVias and very thin geometries - not really something easy and cheap...
Another point is the soldering of these large "beasts": they are massive and require a large thermal throuput oven in order to heat the inner downside of the chip to the reflow temperature while staying inside of the reflow profile curve timing. We have made quite disappointing experiments with an expensive professional rework station. So, to my eyes, you only have the large reflow oven solution to solder these 512 balls chips.

3) Four-layers PCB: the only valid criteria is whether you can afford not powering the BGA chip through power planes - what are the mean and peak currents and such quite complex aspects.

So, I'd never start a home-made-grade PCB with BGA chips larger than 100..150 balls and a pitch that is smaller than 1.0mm
BR
Alain
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rp181
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Postby rp181 » Sat Aug 25, 2012 12:22 pm

I would not even try soldering the BGA package yourself. Your best bet is to have a an assembly house with XRay verification do it for you.

Also, another thing to keep in mind - ports are specific to a core. If you have a cross core peripheral, driving it becomes significantly harder and slower.
SpacedCowboy
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Postby SpacedCowboy » Sat Aug 25, 2012 4:10 pm

Allein wrote:Hi,
As a very experienced complex PCB designer, I would like to bring in some quick remarks on this thread topics:

1) G4 processor: as you maybe not know, the G4 isn't compatible with the new XC processors (L1 / L2 / ...) because of its 1st generation XLink. So, should you want to connect to another XC, then you'd be limited to G4 only ... It's a weak point, sufficient to have me leaving the G4 aside. So, I'm also going towards multiple L1 or L2 for achieving the desired number of XCores and I/Os.
Yes, I know, but the 5v tolerance is very appealing for what I want to use it for. I can use quickswitches if necessary, but I'd prefer not to. I guess all the future XMOS chips will be compatible with the newer standard, so perhaps I ought to rethink that.
Allein wrote:2) 512 balls BGA: I've designed numerous PCBs with tens of large BGAs on-board, and I can tell you that you'll never be able to fan-out the inner signals to the outside using only four layers. Not speaking of connecting the power balls...
Don't forget that, with 0.8mm pitch, you are forced to use MicroVias and very thin geometries - not really something easy and cheap...
Another point is the soldering of these large "beasts": they are massive and require a large thermal throuput oven in order to heat the inner downside of the chip to the reflow temperature while staying inside of the reflow profile curve timing. We have made quite disappointing experiments with an expensive professional rework station. So, to my eyes, you only have the large reflow oven solution to solder these 512 balls chips.
[sigh], yeah, you're right with the 0.8mm thing. I've only done the 1mm (Xilinx FG320) packages to date. I've never had a problem with Spartan 3E chips in that package though, and 320 isn't *too* much smaller than 512, but the ball separation kills it :(

With regard to doing the BGA at home, I think it's down to thermal mass. I've always done BGA as a tiny plug-in board with basically one chip on it. If you're doing large boards with multiple chips on, then yeah, I can see it needing expensive equipment. That's why I don't do that :) my oven wasn't the cheapest one I could buy, it cost ~$1000, but I do try to respect its limitations. I know that's still a dirt-cheap oven ;)

To make sure my alignment is ok, I solder 2 0603 caps at right angles to form an "L" bracket (but otherwise not connected to anything) at two opposite corners of the BGA so it's locked in place. It's a bit fiddly getting that right, but once the USB microscope says everything is lined up perfectly, I put the board in the oven. So far I've had 100% success with this approach.
Allein wrote:Hi
3) Four-layers PCB: the only valid criteria is whether you can afford not powering the BGA chip through power planes - what are the mean and peak currents and such quite complex aspects.

So, I'd never start a home-made-grade PCB with BGA chips larger than 100..150 balls and a pitch that is smaller than 1.0mm
BR
Alain
Well, I've had success several times with about twice that grid size in the past, but it's true I've never tried 512 balls. The largest issue for me is the 0.8mm grid. I hadn't thought that one through - hey it was late and I have a 5 month old baby. My brain's only working on 1.8v power ATM [grin]

In fact, having done a little more research, it seems the XMOS is unlikely to have sufficient oomph alone for what I wanted to do (real time JPEG video compression at SD rates for both PAL and NTSC). I still think there's value in using the XMOS but I will probably want to offload some of the heavy lifting (definitely the DCT, possibly the entropy coding) off to an FPGA. So my focus now is to see if I can get an FPGA to implement the XMOS link protocol, to cut down on the common i/o lines (and also because that'd be more useful than a custom interconnect); if so then the fewer cores in an L{1,2} would be fine, and the whole BGA issue goes out the window (for both XMOS and FPGA) - I still prefer to see what I'm soldering :)

Thanks for the advice :)

Simon
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Folknology
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Postby Folknology » Sat Sep 01, 2012 6:56 pm

You should entertain Xmos Slicekit project, it may provide exactly the kind of thing your looking for in a modular fashion and based around L2s rather than G4s (it would mean loosing 5V tolerance however)

regards
Al

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