XS3 Architecture released

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
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CousinItt
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XS3 Architecture released

Post by CousinItt »

See here: https://www.xmos.ai/file/xmos-xs3-archi ... ion=latest

https://www.xmos.ai/xcore-ai/ also includes details of six variants of XU316, but no live datasheet links yet.


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akp
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Post by akp »

Interesting. The vector unit and the FPU look to be fantastic additions for DSP just taking a quick glance at the new instructions. Clearly the FPU is pretty focused since it doesn't appear to have divider or other features like sqrt; but should be pretty good as long as you don't need ultrafast divide or those other things.

I didn't look deeply at it but is it true that the vector unit is the only thing that can use the full 256b of the bus? 256b memcpy would seems to be a 4x improvement on what is possible on XS2.
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CousinItt
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Post by CousinItt »

The content regarding the 256-bit buffer for each thread and the two lanes for issuing two 16-bit instructions or a single 32-bit instruction seems pretty much identical to the XS2, so I'm not expecting much to change there. Not absolutely sure though.
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akp
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Post by akp »

Right, I meant the instructions to do 256b load and store to the vector unit
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CousinItt
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Post by CousinItt »

Sorry, wrong end of the stick. The document states the memory is 128 bits wide, but that doesn't square with the descriptions of the vector load/store operations. Usually multi-cycle instructions are noted. This diagram in the Linley document shows a 256-bit path.
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