Different Channel Count for In/Out in TDM Frame

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
RitchRock
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Different Channel Count for In/Out in TDM Frame

Post by RitchRock »

In a new project I am using XE-216-512 as more of a standalone DSP / microcontroller (not using USB ref firmware).

My ADC only supports 8 channels TDM per frame up to 192 kHz, but the interface on the other other side supports 4 channels per TDM frame up to 192 kHz. Is it possible to "mix and match"? Maybe I need to use two separate instances?

What I am ultimately trying to do is bring 8 channels of audio in on 4 data lines and 16 channels of audio out with 4 data lines on each side.

I should also mention that I will need to implement I2S TDM Slave, as the 4 channel per TDM frame device on the output side must be the I2S master.

Any advice on the best way to do this would be appreciated.


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akp
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Post by akp »

I am a little confused. On the input are you doing 4x 2 ch I2S or 1 x 8 ch TDM or something else? It seems like you want to do
4x I2S input -> 8 chs on 4 data lines
4x TDM128 output -> 16 chs on 4 data lines
Whatever you're doing it seems like the bit clocks will be different (either 0.5x or 2x the TDM128 bit clock depending on if you're using I2S 2ch or TDM 8ch on the input). So how do you plan to generate the input bit clock? I would say 4x I2S inputs will probably be a bit safer than 1x TDM 8ch input since you'll have a more relaxed timing constraint.
RitchRock
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Post by RitchRock »

The attached block diagram should help. The clocks are generated by the TDM Master. The ADC only supports 8 channels per frame, however the TDM Master does not support 8 channels per frame at higher sampling rates - therein lies my question on the best way to handle that discrepancy.

My actual hardware has 4 data lines between each component of this system. Currently I am running 8 channels into XMOS and 8 channels out to the FPGA using XMOS and ADC as I2S Slaves. If possible, I would like to implement 8 channels into XMOS and 16 channels out to the FPGA.
I2S TDM Question.JPG
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akp
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Post by akp »

Maybe draw out all the clock lines. Since you need 2x your existing bit clock to get the same number of channels, you might want to check if the CS5368 can do 4x I2S outputs with 128 bit clocks per frame rather than 64. That would be straightforward then because you could basically have a 4x TDM 4 input and 4x TDM 4 output but just throw out every 2nd input channel from the CS5368 (as it would effectively use TDM channels 1 and 3 if it would work with 128 bit clocks per I2S frame rather than just 64).
RitchRock
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Post by RitchRock »

I will have to test that. The CS5368 datasheet as perhaps you have seen is vague, simply saying "In Slave Mode, the SCLK/LRCK ratio can be set according to design preference. However, device performance is guaranteed only when using the ratios shown" (64). Anyway, thanks.