LRCK no output under 45M/49M MCLK

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
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akp
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Re: LRCK no output under 45M/49M MCLK

Postby akp » Wed Jan 15, 2020 3:44 pm

I won't say it's impossible to solve it in software. It is very difficult, though. I think you might have a solution if you need to keep your 24 MHz MCLK. You will have to run the XMOS IP as I2S slave rather than I2S master. And set up the TLV320DAC3120 PLL to generate BCLK at 64 * 48 kHz = 3.072 MHz and WCLK at 48 kHz.
twittich
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Postby twittich » Mon Jan 20, 2020 11:56 am

Solved it by changing the routing and calculation of the clocks and works now...
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akp
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Postby akp » Mon Jan 20, 2020 1:45 pm

Great. Running with 24.576 now?

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