PORT_MCLK_COUNT port in USB Audio

[genap]

I have a question about usage of a port PORT_MCLK_COUNT.
I tried to find any description of it in XMOS documentation and Xcore forum with no avail.

The question is about port assignment.
In a reference design it's assigned to the port 16B:

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<Port Location="XS1_PORT_16B" Name="PORT_MCLK_COUNT"/>

The question is about requirements for this port.
What is the required port size?
Can this port be overlapped with other ports (in my case P4E, P4F, which have physical signals assigned)?
In my previous designs I had it overlapped, and it didn't seem to create problems, but I want to make sure.
The processor I use is XUF208-256-TQ64.

Will appreciate any help with this issue.

[rgilio]

I also had the same question. I found this topic https://www.xcore.com/viewtopic.php?t=4302 that clarified some things but I'd still like to have some more defined documentation on expected use/behavior of it since it seems to be used in several examples.

[genap]

The post you mention unfortunately does not explain PORT_MCLK_COUNT functionality and usage, though it provides useful info on ports overlapping.

[mon2]

Can you list a specific reference kit that makes use of this PORT_MCLK_COUNT port for a review?

For us, a good place to start is to study the schematics for the related kit and focus on the 16B port and how it is used in the design.

The XMOS port map spreadsheet is also very helpful to understand how the port widths have their own priority. The (smaller) port widths to the LEFT of the spreadsheet are of HIGHER priority than those to the RIGHT (larger port width).

Please have a quick read of this post on port overlapping:

https://www.xcore.com/viewtopic.php?f=2 ... ing#p33106

[genap]

Thank you for the reply.

The reference design I am using in my current project is sw_usb_audio-[sw]_6.15.2.
The project is app_usb_aud_xk_216_mc, target is XUF208-256-TQ64 (ported).
The PORT_MCLK_COUNT is assigned to XS1_PORT_16B (it seems like a default in all projects so far).
Note: PORT_16B doesn't have any external connections.

There are few things which are not clear to me:
1. The PORT_16B is overlapped with one bit ports as follows:
P16B8 - P1M0
P16B9 - P1N0
P16B10 - P1O0
P16B11 - P1P0
All of these 1 bit ports are used in a project.
Does it matter for the PORT_MCLK_COUNT use?
2. In my previous project (app_usb_aud_skc_su1, target XS1-U8A-64-FB96) only P16B15 is available on a chip, nevertheless assignment of PORT_MCLK_COUNT is the same::

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<Port Location="XS1_PORT_16B" Name="PORT_MCLK_COUNT"/>

Does it mean that PORT_MCL_COUNT can be used even when only one bit of it is available?

[mon2]

1. The PORT_16B is overlapped with one bit ports as follows:
P16B8 - P1M0
P16B9 - P1N0
P16B10 - P1O0
P16B11 - P1P0
All of these 1 bit ports are used in a project.
Does it matter for the PORT_MCLK_COUNT use?

This means that

P1M0 is available for your project but you will lose out on the use of P16B8.
P1N0 is available for your project but you will lose out on the use of P16B9.
P1O0 is available for your project but you will lose out on the use of P16B10.
P1P0 is available for your project but you will lose out on the use of P16B11.

Likewise, if you did R/W data through P16 then P16B8, P16B9, P16B10, P16B11 will not be available due to the smaller width ports being used in your IP.

[mon2]

Does it mean that PORT_MCL_COUNT can be used even when only one bit of it is available?

Yes.

To rephrase the concept, let us say you are working with PB16 which is a 16 bit port but you are making use of smaller width ports that overlap this 16 bit port from say PB0..PB14. That is only PB15 is available and used in this example.

If you output data to this PB16 port then only bit #15 will be seen by the outside world at the physical pin on the CPU. The values of PB0..PB14 will be masked and not steered to the port pins on the CPU. This is due to the smaller overlapping ports stealing away ("waxing") the rest of the port pins. Consider it like inside muxes (multiplexers) ripping away the other port bits.

Just keep in mind that ports on the LEFT have a higher priority than those on the RIGHT. If an overlapping port pin is enabled then the LEFT port width will dominate the RIGHT port widths.

Hope this helps.

[genap]

Does it also mean that it should work in a new design if all of the bits but one in P16B are overlapped by the leftmost (higher priority) used ports?
Meaning that for a proper operation of PORT_MCLK_COUNT at least one not overlapped bit of P16B must be available?

[mon2]

Does it also mean that it should work in a new design if all of the bits but one in P16B are overlapped by the leftmost (higher priority) used ports?
Meaning that for a proper operation of PORT_MCLK_COUNT at least one not overlapped bit of P16B must be available?

Yes. To make use of any ports that are NOT overlapping, you will have to use the original port width which in this example will be the P16B.

When ready with your custom design, please post the relevant pieces of the schematic for a quick review. It is important that you have the proper USB port protection for in-rush current; ESD protection; impedance controlled traces @ 90 ohms for the USB High Speed (480 Mbps) layout; power supply sequencing in the proper order before releasing the #RESET line.

[genap]

mon2, thanks a lot for your explanations,

I still have another related question.
The table below shows ports assignments for ports P8D and P16B.

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X0D40     P8D4     P16B12     RST_X_AD_DA
X0D41     P8D5     P16B13     RST_X_D
X0D42     P8D6     P16B14     LED_BLANK_X_L
X0D43     P8D7     P16B15	

Port 8D overlaps port P16 and has higher priority.
Port P8D4..P8D6 is assigned and has physical signals connected to it.
Port P8D7 has no connections.
The only way for me to assign PORT_MCLK_COUNT is to use port P16B15.
But as far as I understand, even though P8D7 (and so P16B15) is available, I have to assign and address port P8D as a whole, and in this case P16B15 is unavailable.

Is there any way to use P16B15 in this situation?