X200 multichannel FW on X200 explorer

Technical questions regarding the XTC tools and programming with XMOS.
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Dodotronic
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X200 multichannel FW on X200 explorer

Post by Dodotronic »

Hi all,

I'm trying to port the x200 multichannel example on my X200 explorer board with my custom ADC
Since my ADC is not a codec, I don't need the I2C so I commented all the lines reporting I2C so every blocking function is avoided
- The problem is the clock: the multichannel has got a complex clocking for different sampling rate and I don't need it in my board, so I don't know how to set the reference clock from internal . I imagine is it on the audiohw.ec file?
- My configuration is 2i8o8xxxxx_tdm8 probably is this the right configuration from which to start?
- How can I configure my custom IO to communicate with my ADC?

Thanks
Ivano


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Dodotronic
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Post by Dodotronic »

The main difference between the CS5368 and mine LTC2324-16 is that the clock must be driven not continuosly but only when data is collected, moreover the clock cannot be generated externally but by the main XC200 clock. Then I need to synchronize the sampling rate witha timer, ... or that's what I can imagine. Mine ADC too has got 4 output port so probably this is not a problem
Iv
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akp
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Post by akp »

Interesting problem.

Do you mind me asking what sample rate you intend to achieve with this ADC? 2MSPS * 16bit * 4ch = 128Mbps which will exceed the UAC2 standard channel capability (65.5Mbps). I don't know if XMOS supports the UAC2 high bandwidth channel (195Mbps apparently). I don't think I've compiled the code to support that.

If you don't need this particular ADC the easiest solution would be to use a standard audio interface ADC e.g. with TDM or I2S. That would probably be a delta-sigma ADC, however, and you might need a SAR. If you can't use bog standard TDM or I2S then you will have to get into the weeds which will be fun but could be frustrating.
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Dodotronic
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Post by Dodotronic »

The sampling rate of LTC2324 is 500Khz / Channel but I intend to use it for 384Khz /ch and this is supported by UAC2.
The main reason why I chose this ADC is that insted of standard audio codec there's no low pass filter.
I see that the interface is in some aspect similar to the CS5368 so from code I think it's possible to fit this protocol.
The problem resides on the clock, it seems to be impossible for the micro to generate the clock for 384khz sampling rate so the solution available on xc200 multichannels whit external clock generator seems to be mandatory.
The source code seems to be well done but I wasted a lot of time to understand where to change the code to fit a different communication protocol and I hope to find a solution, perhaps because I worked only on ARM and PIC!?!?
Still I don't understand where the input is sampled and stored in the buffer before being passed to the usb handler.
A problem is that when I do some change it is seen no more in windows while it do on android, is there a solution to this?
Iv
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akp
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Post by akp »

Good luck. I'll be interested to hear your results. You should be able to use I2S mode and a fixed clock oscillator, probably 24.576MHz to get 384kHz * 64bits per I2S frame. This would you an MCLK/BCLK ratio of 1.

You will need to implement the circuit shown in "Typical Applications" to reduce the jitter on the CNV\ pin using the retiming flip-flop. I would use the I2S mode and have the LRCLK serve as the CONV input to the retiming flip-flop. So the ADC will start a conversion in the left channel of the I2S frame, and the data will be read on the right channel of the I2S frame (when LRCLK is high).

I think you can gate the ADC SCK simply by AND ing LRCLK and BCLK to get SCK for the chip; it will be stopped low when LRCLK is low for tCONV (i.e. for 0.5/384E3 = 1.3usec which is greater than tCONV = 220ns). Then when LRCLK goes high the SCK will start and data will get clocked out of the ADC.

In theory you could get 2 16 bit samples in during the 32 bit times of the right ADC channel -- which would reduce your data line requirement to 2 -- but you would have to watch out for the LSBit of the 2nd sample (i.e. ch2 on data line 1 and ch 4 on data line 2) since the LRCLK will go low for the LSbit... maybe you could run the I2S in MSB mode if it's possible (so the LRCLK isn't advanced by 1 bit time), that would work to reduce your data line usage. But if you have lots of 1B ports then why bother with the extra work. Just use 4 x 1B ports to read in the data.

So if you can get this running you could probably start with with standard I2S 8 ch 192kHz x 32 bit audio (if you supply the hardware I mentioned above, and use an MCLK/BCLK ratio of 2 so you get a 12.288MHz BCLK instead) -- but chs 1, 3, 5, 7 will be muted and only the 16 MSbits of chs 2, 4, 6, and 8 will be valid. I say start with the 192kHz x 8 x 32bits/sample because it will fit in the UAC2 limit without you mucking around too much with the audio samples or the USB descriptors, it will prove your hardware works and save you wasting time on software. Then you can use standard I2S 4 ch 384kHz x 32 bit audio (MCLK/BCLK=1), this will only use 2 of your data lines but will show that your circuitry is fast enough for 384kHz.

If the hardware works then you have to work on the software so it drops the unused left channels at 384kHz, and then puts the right channels into 4 ch x 384kHz USB audio, maybe 32 bit/sample with the lower 16 bits muted.

If you find my suggestion useful, at least as a kick off point for you -- one thing that I wonder is why you don't want a low pass filter? Are you intending to implement your own anti-aliasing filter or are undersampling e.g. bandpass sampling?
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Dodotronic
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Post by Dodotronic »

Hi
Thanks for the interesting reply
I’m not an expert in xmos so probably I will do some basic question.
Ok for the fixed oscillator.
About the sampling rate you are right I intend to start with 192 k and then go forward.
How is it possible to gate the adc sck with other signal?
The concept is to use 4input lines in order to receive 4channels of data in the same time, reducing the timing restriction, as you sayd 4x1b data.
I produce ultrasonic microphones and till now only one channel using pic or arm uac1 and for multiple channels xmos is mandatory.

Here you can take a look, www.dodotronic.com

I need all the ultrasonic bandwidth for my application. This is the reason why I cannot use standard codecs

Thanks a lot for the tips I will try!!!
Iv
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akp
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Post by akp »

One of the I2S signals is called LRCLK. It operates at the sample rate e.g. 384kHz. Put it to the input of an AND gate, and put the BCLK (bit clk) to the other input of the AND gate. So the output of the AND gate will be zero when LRCLK is zero and it will operate at BCLK frequency (24.576MHz) when LRCLK is high. If you use LRCLK as the CONV input then the SCK to the ADC will be held low when the ADC is converting (first half LRCLK cycle) and it will shift out data for the 2nd half of the LRCLK cycle.

Don't forget to use a flipflop to retime the CONV signal from LRCLK. Otherwise there will be too much jitter and your audio will degrade.

I took a look at your site, very interesting. Good luck.
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Dodotronic
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Post by Dodotronic »

Just to start some test I'm using the XC200 eXplorer board so to have all the pin out.
The main difference between the X200 multichannel is the presence of an external clock going in the pins:
X0D13 and X1D35, from here internally the signal is used to generate the SCLK and LRCLK output
I commented all the I2C functions
Cnfiguration build 1i2o2xxxxx
After connected the 24mhz clock to the pin X0D13 and X1D35 I expect to see the SCLK and LRCLK with my oscilloscope but nothing happens even if the board is seen by windows OS.
Where am I wrong?
Iv
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mon2
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Post by mon2 »

Unable to comment on the audio details as that is not my area but..

1) the USB is working on your XCORE 200 Explorer board due to the external 24 Mhz clock source required for the USB IP. To confirm, remove your external 24 Mhz clock source and the USB should still work. This confirms the explorer kit clock is working ok. This does not confirm that your new 24 Mhz clock feed is ok.

2) if you are feeding a 24 Mhz clock into your Explorer kit via X0D13 then you are overlapping the I2C lines on this kit which should also feature some strong pull-ups. Just a fyi.


Image

Recommend to feed into X1D35 only and write up a small blinky program that will use the input clock from X1D35 to validate this is working ok.


Image
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Dodotronic
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Post by Dodotronic »

I don't understand the point 1; isn't the USB fed from 24mhz external crystal? if I remove the clock I imagine the USB will not work!?! (please consider that I'm working on XMOS only from a week)
I cheked the clock on the pins X0D13 and X1D35 that are tied together and as you sayd I did a small routine

on tile[1] : clock clk = XS1_CLKBLK_5;
on tile[1] : in port p_signal = XS1_PORT_1L;
on tile[1] : out buffered port:32 p_clk_out = XS1_PORT_1O;
configure_clock_src (clk , p_signal);
set_clock_div(clk, 31);
configure_port_clock_output(p_clk_out, clk);
start_clock (clk);

and it works perfectly both on tile 0 with D13 as input and on tile 1 D35 without removing the resistor (probably the BMG160 doesn't affect it).
This states that the input clock is correctly managed.
So this is not the problem, there's something else in the USB audio sw that blobk the generation of LRCLK and BCLK
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