Some ports can not be used as clock outputs?

[wibauxl]

When I simulate the following code:

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#include <platform.h>

out port p1L = XS1_PORT_1L;
out port p1M = XS1_PORT_1M;
out port p4A = XS1_PORT_4A;
clock clk = XS1_CLKBLK_1;

int main(void) {
	int i = 0;
	
	configure_clock_rate(clk , 100 , 10);
	configure_out_port(p4A, clk , 0);
	configure_port_clock_output(p1L , clk);
	configure_port_clock_output(p1M , clk);
	start_clock(clk);
	
	while (1) p4A <: i++;
	
	return 1;
}

I get a few strange things:
1- No clock signal on 1M

test1.png

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test1.png

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2- Going beyond 12.5Mhz, say 16.7Mhz (100/6), the data output timing is not correct anymore.

test2.png

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test2.png

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Surely, running at a frequency of 400Mhz, we should be able to output port data at 50Mhz!?

Are these limits of the simulator or physical limits not quite clearly documented?
Thanks for your help,

[wibauxl]

After using '--dump-ios' running the simulator, I get:

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...
      XS1_PORT_1L: ID = 0x00010b00
        Bit 0: pin 11 'X0D35'
      XS1_PORT_1M: ID = 0x00010c00
        Bit 0: not connected
      XS1_PORT_1N: ID = 0x00010d00
        Bit 0: not connected
      XS1_PORT_1O: ID = 0x00010e00
        Bit 0: not connected
      XS1_PORT_1P: ID = 0x00010f00
        Bit 0: not connected
...

Which probably explains my point 1...
But surely, this is wrong as the documentation of the XS1-64 shows those pins connected and Sparkfun kit has got them as pads!

On top of that, when tracing the pads in the simulator, I can not find pads 36 to 39...

Where can I correct this?
Thanks,

[Woody]

In response to point 2. I can't work out the actual timing on XS1_PORT_1L, but the waveform looks as I would expect it. Within the while(1) loop there are a number of instructions that execute on a 100MHz thread. When clk is running slowly there is enough time to execute these instructions before the next clk pulse. However if clk's frequency is increased there is not quite enough time to execute all the instructions per clk pulse. Because XS1_PORT_4A is updated when a clk pulse occurs, if one is missed, the update to port 4A only occurs on the next clk pulse. The output clock on Port 1L looks right to me.

Why don't you have a look at the assembler instructions in while (1). You could use xobjdump or our XTA tool to do this.