FPGA in the JTAG chain

[nick]

Hi,
we are developping a custom board, in which we have 2x XE216-512-TQ128-I20 and then a Spartan6 FPGA.

Impact tool (Xilinx FPGA programming tool) works smoothly discovering the whole chain, which is composed by 2 unknown devices (XMOS) and the FPGA that could properly be programmed.

Unfortunately the same doesn't happen with the xTag3. We found no way to make xTag3 to recognize any of the connected devices.

Code: Select all

xrun --jtag-speed 10 -l

Available XMOS Devices
----------------------

  ID    Name                    Adapter ID      Devices
  --    ----                    ----------      -------
  0     XMOS XTAG-3             nMl_nEaT        None

Of course physically bypassing the FPGA from the JTAG chain everything works as expected. The 2 XMOS are then recognized by the tool and programmed.

Code: Select all

xrun --jtag-speed 10 -l

Available XMOS Devices
----------------------

  ID    Name                    Adapter ID      Devices
  --    ----                    ----------      -------
  0     XMOS XTAG-3             nMl_nEaT        O[0..1]

We strongly need to find a way to make everything work together without physically modifying the board. This will be essential for us for production and testing.

It's necessary to let the tool know the FPGA presence and how to bypass it. It seems it doesn't happening automatically.
Digging in the forum there are some posts about this matter, but without any useful answer. It's seems that something can be done by customizing the .xn file, but documentation doesn't really help in doing this.
Anyone had had success with the same problem?

[mon2]

Hi. Not sure how much the following comments will help but...

1) the xtag3 low level details are not public

2) xtag2 related h/w and s/w info is posted here:

https://github.com/xcore/proj_xtag2

3) in the past reviewed the jtag interface as documented on the fpga4fun website which has been excellent reading. Using that information, we did manage to use standard gpio pins on the xmos cpu to bit-bang out the ID of the lattice FPGA that was under test (DUT). Respectively, if you study and log what the jtag tool is doing to r/w your target flash, etc. - you should be able to recreate that traffic from scratch. We learned using the zeroplus bus analyzer (and JTAG plug-in) but overall the review was certainly time consuming.

4) if you really want a complete and transparent solution, I think you will have to modify the jtag interconnect chain so that, when you use xtag3 - the xmos cpu can be quickly and transparently indexed for your programming, etc. Vice-versa for your Xilinx tools.

On this topic, you wish to use JTAG to confirm the PCBA is clean and without shorts or strictly for firmware programming? Programming of the flash could be done by asserting reset to tri-state the CPU and assert external signals to reflash your firmware.

Not sure how else you can achieve your goal at this time of writing. Perhaps others have better ideas here..

[CousinItt]

Again, for what it's worth, I've had problems with distribution of the TCK signal in larger systems. If you're not using any buffering on the clock and don't have any other components on the line (e.g. termination components at the far end), you could try just a simple snubbing capacitor, say 33 pF to ground on TCK at the xTAG connector. It may not be a viable long term solution but it might get things working.